VLSI Design for Video Coding

Youn-Long Steve Lin

ISBN 10: 1489983821 / ISBN 13: 9781489983824

Editore: Springer US Sep 2014, 2014

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This item is printed on demand - it takes 3-4 days longer - Neuware -High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing.This book will present VLSI architectural design and chip implementation for high definition H.264/AVC video encoding, using a state-of-the-art video application, with complete VLSI prototype, via FPGA/ASIC. It will serve as an invaluable reference for anyone interested in VLSI design and high-level (EDA) synthesis for video. 188 pp. Englisch.

Codice articolo 9781489983824

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• Titolo: VLSI Design for Video Coding
• Editore: Springer US Sep 2014
• Data di pubblicazione: 2014
• Lingua: Inglese
• ISBN 10: 1489983821
• ISBN 13: 9781489983824
• Rilegatura: Taschenbuch
• Condizione: Neu
• Dimensioni: 235 L x 155 A x 11 P (millimetri) 235 millimetri di larghezza per 155 millimetri di altezza per 11 millimetri di profondità
• Peso: 295 grammi

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Riassunto

High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing.

This book will present VLSI architectural design and chip implementation for high definition H.264/AVC video encoding, using a state-of-the-art video application, with complete VLSI prototype, via FPGA/ASIC. It will serve as an invaluable reference for anyone interested in VLSI design and high-level (EDA) synthesis for video.

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VLSI Design for Video Coding

By:

Youn-Long Lin

Chao-Yang Kao

Jian-Wen Chen

Hung-Chih Kuo

High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing.

This book presents VLSI architectural design and chip implementation for high definition H.264/AVC video encoding with a complete FPGA prototype. It serves as an invaluable reference for anyone interested in VLSI design for video coding.

Presents state-of-the-art VLSI architectural design and chip implementation for high definition H.264/AVC video encoding;

Employs massively parallel processing to deliver 1080pHD, with efficient design that can be prototyped via FPGA;

Every subsystem is presented from standard specification, algorithmic description, design considerations, timing planning, block diagram to test-bench verification;