The Verilog® Hardware Description Language

Philip R. Moorby, Donald E. Thomas

ISBN 10: 147577589X / ISBN 13: 9781475775891

Editore: Springer-Verlag New York Inc., US, 2014

Riguardo questo articolo

xv From the Old to the New xvii Acknowledgments xxi 1 Verilog - A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment (" 5th ed. 2002. Softcover reprint of the original 5th ed. 2002.

Codice articolo LU-9781475775891

Dati bibliografici

• Titolo: The Verilog® Hardware Description Language
• Editore: Springer-Verlag New York Inc., US
• Data di pubblicazione: 2014
• Lingua: Inglese
• ISBN 10: 147577589X
• ISBN 13: 9781475775891
• Rilegatura: Paperback
• Condizione: New
• Dimensioni: 15,6 L x 2,13 A x 23,39 P centimetri 15,6 centimetri di larghezza per 2,13 centimetri di altezza per 23,39 centimetri di profondità

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Riassunto

xv From the Old to the New xvii Acknowledgments xxi 1 Verilog – A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("

Contenuti

Verilog — A Tutorial Introduction.- Logic Synthesis.- Behavioral Modeling.- Concurrent Processes.- Module Hierarchy.- Logic Level Modeling.- Cycle-Accurate Specification.- Advanced Timing.- User-Defined Primitives.- Switch Level Modeling.- Projects.