Verilog Styles for Synthesis of Digital Systems

Smith, David R; Franzon, Paul D

ISBN 10: 0201618605 / ISBN 13: 9780201618600

Editore: Pearson, 2019

A well-loved companion. Corners and cover might show a little wear, and you could find some notes or highlights. The dust jacket might be MIA, it might have been a library book and extras aren't guaranteedâ but the story's all there! Codice articolo PKV.0201618605.G

Riassunto:

This book is designed specifically to make the cutting-edge techniques of digital hardware design more accessible to those just entering the field. The text uses a simpler language (Verilog) and standardizes the methodology to the point where even novices can get medium complex designs through to gate-level simulation in a short period of time. Requires a working knowledge of computer organization, Unix, and X windows. Some knowledge of a programming language such as C or Java is desirable, but not necessary. Features a large number of worked examples and problems--from 100 to 100k gate equivalents--all synthesized and successfully verified by simulation at gate level using the VCS compiled simulator, the FPGA Compiler and Behavioral Compiler available from Synopsys, and the FPGA tool suites from Altera and Xilinx. Basic Language Constructs. Structural and Behavioral Specification. Simulation. Procedural Specification. Design Approaches for Single Modules. Validation of Single Modules. Finite State Machine Styles. Control-Point Writing Style. Managing Complexity--Large Designs. Improving Timing, Area, and Power. Design Compiler. Synthesis to Standard Cells. Synthesis to FPGA. Gate Level Simulation and Testing. Alternative Writing Styles. Mixed Technology Design. For anyone wanting an accessible, accelerated introduction to the cutting-edge tools for Digital Hardware Design.

Dalla quarta di copertina:

The material available within this book is suitable for professionals who have had an introduction to Boolean algebra and computer organization. A working knowledge of Unix and X-windows is necessary, along with some experience with programming languages such as 'C' or Java. The book uses Verilog and standardizing methodology to such a degree that seniors and first year graduate students can see medium complex designs through the gate level simulation in a single semester.

Features:

• The piece covers style recommendations specifically oriented to synthesis, illustrated with practical working examples, and easily accessible to the reader.
• It introduces the use of the simulator and then the synthesizers at the earliest practical point; therefore giving the reader the perspective of working with a small design all the way through high level simulation.
• Large number of examples; from 100-100k gate equivalents.
• Topics covered include; Synopsys, Altera, Xilinx, and the standard cell.

Dati bibliografici

Titolo: Verilog Styles for Synthesis of Digital ...
Casa editrice: Pearson
Data di pubblicazione: 2019
Legatura: Brossura
Condizione: good