Riassunto
For over three decades now, silicon capacity has steadily been doubling every year and a half with equally staggering improvements continuously being observed in operating speeds. This increase in capacity has allowed for more complex systems to be built on a single silicon chip. Coupled with this functionality increase, speed improvements have fueled tremendous advancements in computing and have enabled new multi-media applications. Such trends, aimed at integrating higher levels of circuit functionality are tightly related to an emphasis on compactness in consumer electronic products and a widespread growth and interest in wireless communications and products. These trends are expected to persist for some time as technology and design methodologies continue to evolve and the era of Systems on a Chip has definitely come of age. While technology improvements and spiraling silicon capacity allow designers to pack more functions onto a single piece of silicon, they also highlight a pressing challenge for system designers to keep up with such amazing complexity. To handle higher operating speeds and the constraints of portability and connectivity, new circuit techniques have appeared. Intensive research and progress in EDA tools, design methodologies and techniques is required to empower designers with the ability to make efficient use of the potential offered by this increasing silicon capacity and complexity and to enable them to design, test, verify and build such systems.
Contenuti
Preface. Conference Committees. Optimizing Mixer Noise Performance: A 2.4 GHz Gilbert Downconversion Mixer for W-CDMA Application; S. Li, et al. An Analog Non-Volatile Storage System for Audio Signals with Signal Conditioning for Mobile Communication Devices; G.B. Jackson, et al. A Design of Operational Amplifier for Sigma Delta Modulators Using 0.35um CMOS Process; B. Li, H. Tenhunen. A Lower Power CMOS Micromixer for GHz Wireless Applications; Y. Wu, et al. High Current, Low Voltage Current Mirrors and Applications; S.S. Rajput, S.S. Jamuar. Nonlinearity Analysis of a Short Channel CMOS Circuit for RFIC Applications; Y. Wu, et al. A Fast Parametric Model for Contact-Substrate Coupling; N. Masoumi, et al. A Feature Associative Processor for Image Recognition Based on A-D merged Architecture; A. Iwata, et al. Massively Parallel Intelligent Pixel Implementation of a Zerotree Entropy Video Codec for Multimedia Communications; A.M. Rassau, et al. Implementation of a Wavelet Transform Architecture for Image Processing; C. Diou, et al. Scalable Run Time Reconfigurable Architecture; A. Touhafi, et al. Frontier: A Fast Placement System for FPGAs; R. Tessier. Dynamically Reconfigurable Implementation of Control Circuits; N. Lau, V. Sklyarov. An IEEE Compliant Floating Point MAF; R.V.K. Pillai, et al. Design and Analysis of On-Chip CPU Pipelined Caches; C. Ninos, et al. Synchronous to Asynchronous Conversion - A Case Study: the Blowfish Algorithm Implementation; J.M.S. Alcântara, et al. Clock Distribution Strategy for IP-based Development; R.L. Aguiar, et al. An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures; D.H. Albonesi. Single Ended Pass-TransistorLogic &endash; A Comparison with CMOS and CPL; M. Munteanu, et al. Multithreshold Voltage Technology for Low Power Bus Architecture; A. Rjoub, O. Koufopavlou. Integrating Dynamic Power Management in the Design Flow; A. Mota, et al. Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI; S. Lachowicz, et al. On Defect-Level Estimation and the Clustering Effect; J.T. de Sousa. FASTNR: an Efficient Fault Simulator for Linear and Nonlinear DC Circuits; J.S. Augusto, C.F.B. Almeida. Design Error Diagnosis in Digital Circuits without Error Model; R. Ubar, D. Borrione. Efficient RLC Macromodels for Digital IC Interconnect; B. Tutuianu, et al. A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications; A. Doboli, R. Vemuri. A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements; A. Núñez-Aldana, R. Vemuri. RF Interface Design Using Mixed-Mode Methodology; A. Gallegos, et al. History-Based Dynamic Minimization During BDD Construction; R. Drechsler, W. Günther. Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems; L.P. Carloni, et al. Satisfiability-Based Functional Delay Fault Testing; J. Kim, et al. Verification of Abstracted Instruction Cache of TITAC2: A Case Study; T. Yoneda. Speeding Up Look-up-Table Driven Logic Simulation; R. Murgai, et al. Efficient Verification of Behavioral Models Using Sequential Sampling Technique; T. Chen, et al. Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies; S. Raimbault, et al. A Virtual CMOS Library Approach for East Layout Synthesis; F. Moraes, et al. RT-level Route-and-Place Design Methodology for Interconnect Optimizat
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