Writing Testbenches: Functional Verification of HDL Models Bergeron, Janick

Writing Testbenches: Functional Verification of HDL Models Bergeron, Janick

ISBN 10: 0792377664 / ISBN 13: 9780792377665

Editore: Springer, 2000

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Titolo: Writing Testbenches: Functional Verification...

Casa editrice: Springer

Data di pubblicazione: 2000

Legatura: Rilegato

Condizione: New

Descrizione articolo

Riassunto:

This text first introduces the necessary concepts and tools of verification, then describes a process for carrying out an effective functional verification of a design. This book also presents techniques for applying a stimulus and monitoring the response of a design by abstracting the operations using bus-functional models. The architecture of testbenches built around these bus-functional models is important for minimizing development and maintenance effort. Behavioural modelling is another important concept presented in this book. It is used to parallelize the implementation and verification of a design and to perform more efficient simulations. For many, behavioural modelling is synonymous with synthesizeable or RTL modelling. In this book, the term "behavioural" is used to describe any model that adequately emulates the functionality of a design, usually using non-synthesizeable constructs and coding style. The text focuses on the functional verification of hardware designs using either VHDL or Verilog. The reader should have at least a basic knowledge of one of the languages. Ideally, he or she should have experience in writing synthesizeable models and be familiar with running a simulation using any of the available VHDL or Verilog simulators.

Recensione:

"The bible for techniques in writing effective, readable and reusable Verilog and VHDL testbenches within a best-in-class verification process."
Ben Cohen - VHDLCohen Training