Creating Assertion-Based IP - Integrated Circuits and Systems

Foster, Harry D; Krolnik, Adam C

ISBN 10: 0387366415 / ISBN 13: 9780387366418

Editore: Springer, New York and Berlin, 2008

Riguardo questo articolo

Brand New. First Edition / First Print (number line on copyright page 9 8 7 6 5 4 3 2 1). Hardback copy in glazed boards, no dustjacket as issued. 313pp. B/w graphs and diagrams throughout. This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. It demonstrates a systematic process for formal specification and formal testplanning, and also demonstrates effective use of assertions languages beyond the traditional language construct discussions. Note that there many books published on assertion languages (such as System Verilog assertions and PSL). Yet, none of them discuss the important process of testplanning and using these languages to create verification IP. (23/5).

Codice articolo ABE-1639238291162

Dati bibliografici

• Titolo: Creating Assertion-Based IP - Integrated Circuits and Systems
• Editore: Springer, New York and Berlin
• Data di pubblicazione: 2008
• Lingua: Inglese
• ISBN 10: 0387366415
• ISBN 13: 9780387366418
• Rilegatura: Hardcover
• Edizione: 1st Edition
• Condizione: New
• Condizione della sovraccoperta: No Jacket

Descrizione articolo

Riassunto

This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. It demonstrates a systematic process for formal specification and formal testplanning, and also demonstrates effective use of assertions languages beyond the traditional language construct discussions

Note that there many books published on assertion languages (such as SystemVerilog assertions and PSL). Yet, none of them discuss the important process of testplanning and using these languages to create verification IP. This is the first book published on this subject.

Dalla quarta di copertina

Assertion-based IP is much more than a comprehensive set of related assertions. It is a full-fledged reusable and configurable transaction-level verification component, which is used to detect both interesting and incorrect behaviors. Upon detecting interesting or incorrect behavior, the assertion-based IP alerts other verification components within a simulation environment, which are responsible for taking appropriate action. The focus of this book is to bring the assertion discussion up to a higher level and introduce a process for creating effective, reusable, assertion-based IP, which easily integrates with the users existing verification environment, in other words the testbench infrastructure.

The guiding principles promoted in this book when creating an assertion-based IP monitor are:

• modularityassertion-based IP should have a clear separation between detection and action
  
  
• clarityassertion-based IP should be written initially focusing on capturing intent (versus optimizations)

A unique feature of this book is the fully worked out, detailed examples. The concepts presented in the book are drawn from the authors experience developing assertion-based IP, as well as general assertion-based techniques. Creating Assertion-Based IP is an important resource for design and verification engineers.

From the Foreword:

Creating Assertion-Based IP " reduces to process the creation of one of the most valuable kinds of VIP: assertion-based VIP This book will serve as a valuable reference for years to come."

Andrew Piziali, Sr. Design Verification Engineer
Co-Author, ESL Design and Verification: A Prescription for Electronic System Level Methodology
Author, Functional Verification Coverage Measurement and Analysis