A Guide to VHDL Syntax: Based on the New IEEE Std 1076-1993

Bhasker, Jayaram [J.]

ISBN 10: 0133243516 / ISBN 13: 9780133243512

Editore: Pearson College Div, Englewood Cliffs

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Hardcover Edition in Very Good condition. The covers are in great shape with only a hint of shelf wear. The binding is in good shape. Abrasion to ends papers and paste-downs. The interior pages are clean and unmarked. The book will be carefully packaged for shipment for protection from the elements. USPS electronic tracking number issued free of charge. VHDL is clearly becoming the defacto standard as an electronic hardware description language yet the bible of VHDL, the large and complex Language Reference Manual (LRM), is exceptionally cumbersome, if not difficult, to use various parts of the syntax for major constructs are spread in disparate sections throughout the Manual. Designed to alleviate such problems and frustrations, this guide describes the complete syntax of the IEEE Std 1076-1993 version of VHDL showing the complete syntax of major VHDL constructs and sub-constructs in an easy-to-read manner, with clear examples of each. MARKET: A reference for anyone writing VHDL models or using VHDL in CAD development. Codice articolo 14526

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Titolo: A Guide to VHDL Syntax: Based on the New ...

Casa editrice: Pearson College Div, Englewood Cliffs

Legatura: Hardcover

Condizione: Very Good

Condizione sovraccoperta: No Jacket

Edizione: First Edition.

Descrizione articolo

Riassunto:

Vhdl is clearly becoming the defacto standard as an electronic hardware description language — yet the bible of Vhdl, the large and complex Language Reference Manual (Lrm), is exceptionally cumbersome, if not difficult, to use — various parts of the syntax for major constructs are spread in disparate sections throughout the Manual. Designed to alleviate such problems and frustrations, this guide describes the complete syntax of the Ieee Std 1076-1993 version of Vhdl — showing the complete syntax of major Vhdl constructs and sub-constructs in an easy-to-read manner, with clear examples of each. A reference for anyone writing Vhdl models or using Vhdl in Cad development.

L'autore:

J. Bhasker (Ph.D., University of Minnesota) is a member of the Technical Staff at AT&T Bell Laboratories, Allentown, PA, where he is currently working on a high-level synthesis tool that would synthesize net-lists from C or VHDL behavioral descriptions. He teaches courses on VHDL and VHDL Synthesis to internal AT&T designers as well as at Lehigh University. He is the author of A VHDL Primer (Prentice Hall) and numerous professional papers and articles. Dr. Bhasker has served as Program Committee member and session chair for the VHDL International Users Forum and was the recipient of the Honeywell Excel Pioneer Award (1987).