Microprocessor-Based Parallel Architecture for Reliable Digital Signal Processing Systems (CRC Press Computer Engineering Series)

George, Alan D.; Hawkes, Lois Wright

ISBN 10: 0849371767 / ISBN 13: 9780849371769

Editore: CRC Press, Inc., Boca Raton, FL, U.S.A., 1992

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Hardcover with very slight signs of corner wear and contents in very good clean condition. Previous owner's name on FEP. Profusely illustrated by diagrams and tables. No dust jacket. T.

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Dati bibliografici

• Titolo: Microprocessor-Based Parallel Architecture for Reliable Digital Signal Processing Systems (CRC Press Computer Engineering Series)
• Editore: CRC Press, Inc., Boca Raton, FL, U.S.A.
• Data di pubblicazione: 1992
• Lingua: Inglese
• ISBN 10: 0849371767
• ISBN 13: 9780849371769
• Rilegatura: hardcover
• Edizione: First Edition, First Printing.
• Condizione: Very Good
• Condizione della sovraccoperta: No Dust Jacket
• Tipo di libro: Used
• Cataloghi dei venditori:
  • Science - Electronics

Descrizione articolo

Riassunto

This book presents a distributed multiprocessor architecture that is faster, more versatile, and more reliable than traditional single-processor architectures. It also describes a simulation technique that provides a highly accurate means for building a prototype system in software. The system prototype is studied and analyzed using such DSP applications as digital filtering and fast Fourier transforms. The code is included as well, which allows others to build software prototypes for their own research systems. The design presented in Microprocessor-Based Parallel Architecture for Reliable Digital Signal Processing Systems introduces the concept of a dual-mode architecture that allows users a dynamic choice between either a conventional or fault-tolerant system as application requirements dictate. This volume is a "must have" for all professionals in digital signal processing, parallel and distributed computer architecture, and fault-tolerant computing.

Contenuti

INTRODUCTION. STATEMENT OF THE PROBLEM. Fault Tolerance. Performance. METHOD OF ATTACK. FAULT-TOLERANT COMPUTING. BASIC DEFINITIONS. FAULT TOLERANCE OVERVIEW. REDUNDANCY TECHNIQUES. Hardware Redundancy. Software Redundancy. Information Redundancy. Time Redundancy. FAULT-TOLERANT COMMUNICATION ARCHITECTURES. Reliable Shared Buses. Shared-Memory Interconnection Networks. Loop Architectures. Tree Networks. Dynamically Reconfigurable Networks. Binary Cube Interconnection Networks. Graph Networks. ATOMIC TRANSACTIONS. COMMUNICATION NETWORK PROPERTIES. EXAMPLES OF FAULT-TOLERANT SYSTEMS. Tandem Non-Stop Computer System. Stratus Computer System. Electronic Switching System. Space Shuttle Computer System. Fault-Tolerant Multiprocessor. Software Implemented Fault Tolerance. August Systems Industrial Control Computers. The C.vmp System. PARALLEL COMPUTING. PARALLEL PROCESSING OVERVIEW AND DEFINITIONS. PARALLEL ARCHITECTURE MODELS. OPERATING SYSTEM OVERVIEW. REAL-TIME COMPUTING OVERVIEW. DIGITAL SIGNAL PROCESSING AND PROCESSORS. DIGITAL SIGNAL PROCESSING OVERVIEW. BASIC ALGORITHMS. Digital Filters. Fast Fourier Transforms. DIGITAL SIGNAL PROCESSING MICROPROCESSORS. Specialized Arithmetic Hardware. Multiple Buses. Pipelining. THE DSP96002 DIGITAL SIGNAL PROCESSOR. Introduction. Programming Model. Addressing Modes. Instruction Set. Host Interfacing. SYSTEM DESIGN. PREMISES AND GOALS. DSP IMPLEMENTATION CONSIDERATIONS. Digital Filtering. Fast Fourier Transformations. REDUNDANCY CONSIDERATIONS. COMMUNICATION ARCHITECTURE CONSIDERATIONS. STATIC REDUNDANCY CONSIDERATIONS. Hardware-Based vs. Software-Based Voting. Single-Output Fault-Tolerant Voting. Input Selection. FAULT-TOLERANT CLOCK SYNCHRONIZATION. COMMUNICATION PRIMITIVES. SYSTEM INTERFACE AND COMMUNICATION DESIGN. Memory Interface Model. PE-to-PE Interfacing. PE-to-Output Interfacing. Input-to-PE Interfacing. DESIGN ENHANCEMENTS FOR A DUAL-MODE ARCHITECTURE. Dual-Mode Final-Stage Output Interface Design. Dual-Mode Initial-Stage Input Interface Design. SYSTEM SIMULATION. SIMULATION LIBRARY SUPPORT. IEEE SINGLE-PRECISION CONVERSION. SYSTEM SIMULATION OVERVIEW. SIMULATION OF PE-TO-PE COMMUNICATION. SIMULATION OF PE-TO-OUTPUT COMMUNICATION. SIMULATION OF INPUT-TO-PE COMMUNICATION. PRELIMINARY TEST AND EVALUATION. COMMUNICATION PRIMITIVES. DATA PROPAGATION. DIGITAL FILTERING. FAST FOURIER TRANSFORMATIONS. FAULT INJECTION AND ANALYSIS. ANALYTICAL ANALYSIS. CONCLUSIONS. APPENDIX A: MULTIPROCESSOR SIMULATION LIBRARY FUNCTIONS. APPENDIX B: SIMULATION SOFTWARE LISTINGS. APPENDIX C: SYSTEM MACRO AND EQUATE SOFTWARE LISTINGS. APPENDIX D: PRELIMINARY TEST SOFTWARE LISTINGS. BIBLIOGRAPHY. INDEX.