J sivaraman (48 risultati)

Hardcover. Condizione: Very Good. Condizione sovraccoperta: Good. 1st Edition. Hardcover with dust jacket; full green cloth over boards with gold lettering stamped on spine. Green matte DJ. Sewn binding. 426 pages, with dozens of b/w photographs and many maps; glossary, appendices, bibliography, index. Stated 1st Edition, 1st Printing. CONDITION: Book NEAR FINE, binding square and tight, pages unmarked, no names; foxing on end papers; DJ GOOD, wrappers rubbed and creased, quarter-sized chips at head and foot of spine and lower back corner. corner chips, 3-inch closed tear at base of spine; not clipped, protected in a clear archival (Mylar) cover. CONTENT: Description of farmers and farming conditions in select regions of India, adding to the areas covered in Volume 1. >Guaranteed prompt shipment, secure packaging, and free tracking. …

Hardcover. Condizione: Good - Cash. No Jacket. General use wear, surface and edges rubbed. Corners bumped and show wear. Pages show reader wear. P/o stamp inside. Foxing/yellowing to the end pages. Stock photos may not look exactly like the book.

hardcover. Condizione: Very Good. No Dust Jacket. First Edition. Hardback in very good condition. Printed boards, a little scuffed; previous owner's name on FEP, no jacket as issued; contents clean, sound, bright. TPW. Used.

Hardcover. Condizione: Like New. Like NewLIKE NEW. book.

Condizione: New.

hardcover. Condizione: New. In shrink wrap. Looks like an interesting title.

Condizione: As New. Unread book in perfect condition.

Condizione: New. In English.

Condizione: New. In English.

Condizione: New.

Condizione: Gut. Zustand: Gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.…

Condizione: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . .…

Condizione: As New. Unread book in perfect condition.

Condizione: New. pp. 176.

Condizione: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . . Books ship from the US and Ireland.…

Condizione: New.

Condizione: As New. Unread book in perfect condition.

Condizione: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.…

Condizione: As New. Unread book in perfect condition.

Condizione: New.

Condizione: New.

Condizione: New.

Condizione: New.

Paperback. Condizione: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

HRD. Condizione: New. New Book. Shipped from UK. Established seller since 2000.

HRD. Condizione: New. New Book. Shipped from UK. Established seller since 2000.

Condizione: New.

Hardback. Condizione: New. New copy - Usually dispatched within 4 working days.

Condizione: New. In English.

Condizione: New.