jan vanhoof (41 risultati)

Hardcover. Condizione: Bon. Ancien livre de bibliothèque. Légères traces d'usure sur la couverture. Edition 1993. Ammareal reverse jusqu'à 15% du prix net de cet article à des organisations caritatives. ENGLISH DESCRIPTION Book Condition: Used, Good. Former library book. Slight signs of wear on the cover. Edition 1993. Ammareal gives back up to 15% of this item's net price to charity organizations.

Condizione: Very Good. Most items will be dispatched the same or the next working day. A copy that has been read, but is in excellent condition. Pages are intact and not marred by notes or highlighting. The spine remains undamaged.

Condizione: very good. Gut/Very good: Buch bzw. Schutzumschlag mit wenigen Gebrauchsspuren an Einband, Schutzumschlag oder Seiten. / Describes a book or dust jacket that does show some signs of wear on either the binding, dust jacket or pages.

Condizione: New.

hardcover. Condizione: Very Good. Condizione sovraccoperta: No Dust Jacket. Name from previous owner on FEP. Instances of extremely light wear to edges of spine: several very small nicks and some softening of corners. Covers also have very light surface wear in some places. Spine feels rigid and secure. Pages are clean and crisp, and printing is tight, clean and bright throughout. No dust jacket. MB. Used.

hardcover. Condizione: Very Good. Condizione sovraccoperta: No Dust Jacket. Name from previous owner on first page. Minor bumps to the ends of the spine. Inside, pages are clean and crisp, and printing is tight, clean and bright throughout. MB. Used.

Condizione: new.

Condizione: Very good.

Condizione: Very good.

hardcover. Condizione: New. In shrink wrap. Looks like an interesting title!

Condizione: Gut. Zustand: Gut | Seiten: 310 | Sprache: Englisch | Produktart: Bücher | High-Level Synthesis for Real-Time Digital Signal Processing is a comprehensive reference work for researchers and practicing ASIC design engineers. It focuses on methods for compiling complex, low to medium throughput DSP system, and on the implementation of these methods in the CATHEDRAL-II compiler. The emergence of independent silicon foundries, the reduced price of silicon real estate and the shortened processing turn-around time bring silicon technology within reach of system houses. Even for low volumes, digital systems on application-specific integrated circuits (ASICs) are becoming an economically meaningful alternative for traditional boards with analogue and digital commodity chips. ASICs cover the application region where inefficiencies inherent to general-purpose components cannot be tolerated. However, full-custom handcrafted ASIC design is often not affordable in this competitive market. Long design times, a high development cost for alow production volume, the lack of silicon designers and the lack of suited design facilities are inherent difficulties to manual full-custom chip design. To overcome these drawbacks, complex systems have to be integrated in ASICs much faster and without losing too much efficiency in silicon area and operation speed compared to handcrafted chips. The gap between system design and silicon design can only be bridged by new design (CAD). The idea of a silicon compiler, translating a behavioural system specification directly into silicon, was born from the awareness that the ability to fabricate chips is indeed outrunning the ability to design them. At this moment, CAD is one order of magnitude behind schedule. Conceptual CAD is the keyword to mastering the design complexity in ASIC design and the topic of this book.

Condizione: New.

Condizione: New.

Condizione: New.

Condizione: New. In.

Condizione: New. In.

Condizione: Very good.

Condizione: New.

Condizione: As New. Unread book in perfect condition.

Condizione: As New. Unread book in perfect condition.

Condizione: New. pp. 312.

Condizione: New. pp. 312.

Condizione: New. A comprehensive reference work for researchers and practicing ASIC design engineers. This book focuses on methods for compiling complex, low to medium throughput DSP system, and on the implementation of these methods in the CATHEDRAL-II compiler. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 302 pages, biography. BIC Classification: TJFC; TJK. Category: (P) Professional & Vocational; (XV) Technical / Manuals. Dimension: 234 x 156 x 19. Weight in Grams: 615. . 1993. Hardback. . . . .

Buch. Condizione: Neu. Neuware -High-Level Synthesis for Real-Time Digital Signal Processing is a comprehensive reference work for researchers and practicing ASIC design engineers. It focuses on methods for compiling complex, low to medium throughput DSP system, and on the implementation of these methods in the CATHEDRAL-II compiler.The emergence of independent silicon foundries, the reduced price of silicon real estate and the shortened processing turn-around time bring silicon technology within reach of system houses. Even for low volumes, digital systems on application-specific integrated circuits (ASICs) are becoming an economically meaningful alternative for traditional boards with analogue and digital commodity chips.ASICs cover the application region where inefficiencies inherent to general-purpose components cannot be tolerated. However, full-custom handcrafted ASIC design is often not affordable in this competitive market. Long design times, a high development cost for alow production volume, the lack of silicon designers and the lack of suited design facilities are inherent difficulties to manual full-custom chip design.To overcome these drawbacks, complex systems have to be integrated in ASICs much faster and without losing too much efficiency in silicon area and operation speed compared to handcrafted chips. The gap between system design and silicon design can only be bridged by new design (CAD). The idea of a silicon compiler, translating a behavioural system specification directly into silicon, was born from the awareness that the ability to fabricate chips is indeed outrunning the ability to design them. At this moment, CAD is one order of magnitude behind schedule. Conceptual CAD is the keyword to mastering the design complexity in ASIC design and the topic of this book.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 310 pp. Englisch.

Taschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - High-Level Synthesis for Real-Time Digital Signal Processing is a comprehensive reference work for researchers and practicing ASIC design engineers. It focuses on methods for compiling complex, low to medium throughput DSP system, and on the implementation of these methods in the CATHEDRAL-II compiler. The emergence of independent silicon foundries, the reduced price of silicon real estate and the shortened processing turn-around time bring silicon technology within reach of system houses. Even for low volumes, digital systems on application-specific integrated circuits (ASICs) are becoming an economically meaningful alternative for traditional boards with analogue and digital commodity chips. ASICs cover the application region where inefficiencies inherent to general-purpose components cannot be tolerated. However, full-custom handcrafted ASIC design is often not affordable in this competitive market. Long design times, a high development cost for alow production volume, the lack of silicon designers and the lack of suited design facilities are inherent difficulties to manual full-custom chip design. To overcome these drawbacks, complex systems have to be integrated in ASICs much faster and without losing too much efficiency in silicon area and operation speed compared to handcrafted chips. The gap between system design and silicon design can only be bridged by new design (CAD). The idea of a silicon compiler, translating a behavioural system specification directly into silicon, was born from the awareness that the ability to fabricate chips is indeed outrunning the ability to design them. At this moment, CAD is one order of magnitude behind schedule. Conceptual CAD is the keyword to mastering the design complexity in ASIC design and the topic of this book.

Buch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - High-Level Synthesis for Real-Time Digital Signal Processing is a comprehensive reference work for researchers and practicing ASIC design engineers. It focuses on methods for compiling complex, low to medium throughput DSP system, and on the implementation of these methods in the CATHEDRAL-II compiler. The emergence of independent silicon foundries, the reduced price of silicon real estate and the shortened processing turn-around time bring silicon technology within reach of system houses. Even for low volumes, digital systems on application-specific integrated circuits (ASICs) are becoming an economically meaningful alternative for traditional boards with analogue and digital commodity chips. ASICs cover the application region where inefficiencies inherent to general-purpose components cannot be tolerated. However, full-custom handcrafted ASIC design is often not affordable in this competitive market. Long design times, a high development cost for alow production volume, the lack of silicon designers and the lack of suited design facilities are inherent difficulties to manual full-custom chip design. To overcome these drawbacks, complex systems have to be integrated in ASICs much faster and without losing too much efficiency in silicon area and operation speed compared to handcrafted chips. The gap between system design and silicon design can only be bridged by new design (CAD). The idea of a silicon compiler, translating a behavioural system specification directly into silicon, was born from the awareness that the ability to fabricate chips is indeed outrunning the ability to design them. At this moment, CAD is one order of magnitude behind schedule. Conceptual CAD is the keyword to mastering the design complexity in ASIC design and the topic of this book.

Paperback. Condizione: Brand New. 312 pages. 9.00x6.50x0.71 inches. In Stock.

Hardcover. Condizione: Like New. Like New. book.

Condizione: New. A comprehensive reference work for researchers and practicing ASIC design engineers. This book focuses on methods for compiling complex, low to medium throughput DSP system, and on the implementation of these methods in the CATHEDRAL-II compiler. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 302 pages, biography. BIC Classification: TJFC; TJK. Category: (P) Professional & Vocational; (XV) Technical / Manuals. Dimension: 234 x 156 x 19. Weight in Grams: 615. . 1993. Hardback. . . . . Books ship from the US and Ireland.

Paperback. Condizione: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.