9780898383003 - a systolic array optimizing compiler: 64 di lam, monica s. (10 risultati)
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Da: Books From California, Simi Valley, CA, U.S.A.Books From California
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hardcover. Condizione: Very Good.
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Da: Ria Christie Collections, Uxbridge, Regno UnitoRia Christie Collections
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Condizione: New. In.
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Da: Books Puddle, New York, NY, U.S.A.Books Puddle
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Condizione: New. pp. 228.
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Da: Kennys Bookshop and Art Galleries Ltd., Galway, GY, IrlandaKennys Bookshop and Art Galleries Ltd.
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Condizione: New. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 202 pages, biography. BIC Classification: PHDS. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 239 x 162 x 17. Weight in Grams: 482. . 1989. Hardback. . . . .
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Da: Kennys Bookstore, Olney, MD, U.S.A.Kennys Bookstore
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EUR 166,76
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Condizione: New. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 202 pages, biography. BIC Classification: PHDS. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 239 x 162 x 17. Weight in Grams: 482. . 1989. Hardback. . . . . Books ship from th…e US and Ireland.
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Da: AHA-BUCH GmbH, Einbeck, GermaniaAHA-BUCH GmbH
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EUR 114,36
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Buch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon University in 1987. It documents the research and results of the compiler technology developed for the Warp machine. Warp is a systolic array built out of custom, high-…performance processors, each of which can execute up to 10 million floating-point operations per second (10 MFLOPS). Under the direction of H. T. Kung, the Warp machine matured from an academic, experimental prototype to a commercial product of General Electric. The Warp machine demonstrated that the scalable architecture of high-peiformance, programmable systolic arrays represents a practical, cost-effective solu tion to the present and future computation-intensive applications. The success of Warp led to the follow-on iWarp project, a joint project with Intel, to develop a single-chip 20 MFLOPS processor. The availability of the highly integrated iWarp processor will have a significant impact on parallel computing. One of the major challenges in the development of Warp was to build an optimizing compiler for the machine. First, the processors in the xx A Systolic Array Optimizing Compiler array cooperate at a fine granularity of parallelism, interaction between processors must be considered in the generation of code for individual processors. Second, the individual processors themselves derive their performance from a VLIW (Very Long Instruction Word) instruction set and a high degree of internal pipelining and parallelism. The compiler contains optimizations pertaining to the array level of parallelism, as well as optimizations for the individual VLIW processors.
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Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermaniaBuchWeltWeit Ludwig Meier e.K.
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EUR 106,99
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Buch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon University in 1987. It documents the research and results of the compiler technology developed for the Warp machine. Warp is a systolic array built out…of custom, high-performance processors, each of which can execute up to 10 million floating-point operations per second (10 MFLOPS). Under the direction of H. T. Kung, the Warp machine matured from an academic, experimental prototype to a commercial product of General Electric. The Warp machine demonstrated that the scalable architecture of high-peiformance, programmable systolic arrays represents a practical, cost-effective solu tion to the present and future computation-intensive applications. The success of Warp led to the follow-on iWarp project, a joint project with Intel, to develop a single-chip 20 MFLOPS processor. The availability of the highly integrated iWarp processor will have a significant impact on parallel computing. One of the major challenges in the development of Warp was to build an optimizing compiler for the machine. First, the processors in the xx A Systolic Array Optimizing Compiler array cooperate at a fine granularity of parallelism, interaction between processors must be considered in the generation of code for individual processors. Second, the individual processors themselves derive their performance from a VLIW (Very Long Instruction Word) instruction set and a high degree of internal pipelining and parallelism. The compiler contains optimizations pertaining to the array level of parallelism, as well as optimizations for the individual VLIW processors. 228 pp. Englisch.
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Da: Majestic Books, Hounslow, Regno UnitoMajestic Books
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EUR 146,92
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Condizione: New. Print on Demand pp. 228 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam.
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Da: Biblios, frankfurt am main, HESSE, GermaniaBiblios
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EUR 150,61
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Condizione: New. PRINT ON DEMAND pp. 228.
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Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germaniabuchversandmimpf2000
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 106,99
EUR 60,00 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Buch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon University in 1987. It documents the research and results of the compiler technology developed for the Warp machine. Warp is a systolic array built out of c…ustom, high-performance processors, each of which can execute up to 10 million floating-point operations per second (10 MFLOPS). Under the direction of H. T. Kung, the Warp machine matured from an academic, experimental prototype to a commercial product of General Electric. The Warp machine demonstrated that the scalable architecture of high-peiformance, programmable systolic arrays represents a practical, cost-effective solu tion to the present and future computation-intensive applications. The success of Warp led to the follow-on iWarp project, a joint project with Intel, to develop a single-chip 20 MFLOPS processor. The availability of the highly integrated iWarp processor will have a significant impact on parallel computing. One of the major challenges in the development of Warp was to build an optimizing compiler for the machine. First, the processors in the xx A Systolic Array Optimizing Compiler array cooperate at a fine granularity of parallelism, interaction between processors must be considered in the generation of code for individual processors. Second, the individual processors themselves derive their performance from a VLIW (Very Long Instruction Word) instruction set and a high degree of internal pipelining and parallelism. The compiler contains optimizations pertaining to the array level of parallelism, as well as optimizations for the individual VLIW processors.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 228 pp. Englisch.
