9781461289616 - a systolic array optimizing compiler: 64 di lam, monica s. s. (9 risultati)
- Brossura
Da: Ria Christie Collections, Uxbridge, Regno UnitoRia Christie Collections
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 116,61
EUR 14,00 spedizioneSpedito da Regno Unito a U.S.A.Quantità: Più di 20 disponibili
Condizione: New. In.
- Brossura
Da: Books Puddle, New York, NY, U.S.A.Books Puddle
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 143,78
EUR 3,45 spedizioneSpedito in U.S.A.Quantità: 4 disponibili
Condizione: New. pp. 228.
- Brossura
Da: AHA-BUCH GmbH, Einbeck, GermaniaAHA-BUCH GmbH
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 112,77
EUR 61,77 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Taschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon University in 1987. It documents the research and results of the compiler technology developed for the Warp machine. Warp is a systolic array built out of custom…, high-performance processors, each of which can execute up to 10 million floating-point operations per second (10 MFLOPS). Under the direction of H. T. Kung, the Warp machine matured from an academic, experimental prototype to a commercial product of General Electric. The Warp machine demonstrated that the scalable architecture of high-peiformance, programmable systolic arrays represents a practical, cost-effective solu tion to the present and future computation-intensive applications. The success of Warp led to the follow-on iWarp project, a joint project with Intel, to develop a single-chip 20 MFLOPS processor. The availability of the highly integrated iWarp processor will have a significant impact on parallel computing. One of the major challenges in the development of Warp was to build an optimizing compiler for the machine. First, the processors in the xx A Systolic Array Optimizing Compiler array cooperate at a fine granularity of parallelism, interaction between processors must be considered in the generation of code for individual processors. Second, the individual processors themselves derive their performance from a VLIW (Very Long Instruction Word) instruction set and a high degree of internal pipelining and parallelism. The compiler contains optimizations pertaining to the array level of parallelism, as well as optimizations for the individual VLIW processors.
- Brossura
Da: Mispah books, Redhill, SURRE, Regno UnitoMispah books
Contatta il venditoreVenditore con 4 stelleCondizione: Usato - Come nuovo
EUR 182,95
EUR 29,21 spedizioneSpedito da Regno Unito a U.S.A.Quantità: 1 disponibili
Paperback. Condizione: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
- Brossura
- Print on Demand
Da: Brook Bookstore On Demand, Napoli, NA, ItaliaBrook Bookstore On Demand
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 86,24
EUR 5,50 spedizioneSpedito da Italia a U.S.A.Quantità: Più di 20 disponibili
Condizione: new. Questo è un articolo print on demand.
- Brossura
- Print on Demand
Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermaniaBuchWeltWeit Ludwig Meier e.K.
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 106,99
EUR 23,00 spedizioneSpedito da Germania a U.S.A.Quantità: 2 disponibili
Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon University in 1987. It documents the research and results of the compiler technology developed for the Warp machine. Warp is a systolic array bui…lt out of custom, high-performance processors, each of which can execute up to 10 million floating-point operations per second (10 MFLOPS). Under the direction of H. T. Kung, the Warp machine matured from an academic, experimental prototype to a commercial product of General Electric. The Warp machine demonstrated that the scalable architecture of high-peiformance, programmable systolic arrays represents a practical, cost-effective solu tion to the present and future computation-intensive applications. The success of Warp led to the follow-on iWarp project, a joint project with Intel, to develop a single-chip 20 MFLOPS processor. The availability of the highly integrated iWarp processor will have a significant impact on parallel computing. One of the major challenges in the development of Warp was to build an optimizing compiler for the machine. First, the processors in the xx A Systolic Array Optimizing Compiler array cooperate at a fine granularity of parallelism, interaction between processors must be considered in the generation of code for individual processors. Second, the individual processors themselves derive their performance from a VLIW (Very Long Instruction Word) instruction set and a high degree of internal pipelining and parallelism. The compiler contains optimizations pertaining to the array level of parallelism, as well as optimizations for the individual VLIW processors. 228 pp. Englisch.
- Brossura
- Print on Demand
Da: Majestic Books, Hounslow, Regno UnitoMajestic Books
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 148,67
EUR 7,60 spedizioneSpedito da Regno Unito a U.S.A.Quantità: 4 disponibili
Condizione: New. Print on Demand pp. 228 49:B&W 6.14 x 9.21 in or 234 x 156 mm (Royal 8vo) Perfect Bound on White w/Gloss Lam.
- Brossura
- Print on Demand
Da: Biblios, frankfurt am main, HESSE, GermaniaBiblios
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 152,58
EUR 9,95 spedizioneSpedito da Germania a U.S.A.Quantità: 4 disponibili
Condizione: New. PRINT ON DEMAND pp. 228.
- Brossura
- Print on Demand
Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germaniabuchversandmimpf2000
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 106,99
EUR 60,00 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon University in 1987. It documents the research and results of the compiler technology developed for the Warp machine. Warp is a systolic array built o…ut of custom, high-performance processors, each of which can execute up to 10 million floating-point operations per second (10 MFLOPS). Under the direction of H. T. Kung, the Warp machine matured from an academic, experimental prototype to a commercial product of General Electric. The Warp machine demonstrated that the scalable architecture of high-peiformance, programmable systolic arrays represents a practical, cost-effective solu tion to the present and future computation-intensive applications. The success of Warp led to the follow-on iWarp project, a joint project with Intel, to develop a single-chip 20 MFLOPS processor. The availability of the highly integrated iWarp processor will have a significant impact on parallel computing. One of the major challenges in the development of Warp was to build an optimizing compiler for the machine. First, the processors in the xx A Systolic Array Optimizing Compiler array cooperate at a fine granularity of parallelism, interaction between processors must be considered in the generation of code for individual processors. Second, the individual processors themselves derive their performance from a VLIW (Very Long Instruction Word) instruction set and a high degree of internal pipelining and parallelism. The compiler contains optimizations pertaining to the array level of parallelism, as well as optimizations for the individual VLIW processors.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 228 pp. Englisch.
