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Aggiungi al carrelloCondizione: New. In.
Lingua: Inglese
Editore: Springer International Publishing AG, CH, 2014
ISBN 10: 3319032208 ISBN 13: 9783319032207
Da: Rarewaves.com USA, London, LONDO, Regno Unito
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Aggiungi al carrelloHardback. Condizione: New. 2014 ed.
Lingua: Inglese
Editore: Springer International Publishing, 2014
ISBN 10: 3319032208 ISBN 13: 9783319032207
Da: moluna, Greven, Germania
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Aggiungi al carrelloCondizione: New. Provides a systematic approach to on-chip ESD protection for system-level IC pinsDescribes a system-level co-design methodology, which uses external system level ESD protection components, together with on-chip ESD protection structureInclu.
Condizione: New. pp. 340.
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Aggiungi al carrelloHardcover. Condizione: Brand New. 2014 edition. 320 pages. 9.25x6.25x1.00 inches. In Stock.
Lingua: Inglese
Editore: Springer International Publishing, Springer International Publishing, 2014
ISBN 10: 3319032208 ISBN 13: 9783319032207
Da: AHA-BUCH GmbH, Einbeck, Germania
EUR 117,69
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Aggiungi al carrelloBuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection. It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD protection design is demonstrated with representative case studies which are analyzed with various numerical simulations and ESD testing. The overall methodology for IC-system ESD co-design is presented as a step-by-step procedure that involves both ESD testing and numerical simulations.
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Aggiungi al carrelloHardcover. Condizione: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
Lingua: Inglese
Editore: Springer International Publishing AG, CH, 2014
ISBN 10: 3319032208 ISBN 13: 9783319032207
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Aggiungi al carrelloHardback. Condizione: New. 2014 ed.
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Aggiungi al carrelloCondizione: new. Questo è un articolo print on demand.
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Aggiungi al carrelloHardcover. Condizione: Brand New. 2014 edition. 320 pages. 9.25x6.25x1.00 inches. In Stock. This item is printed on demand.
Lingua: Inglese
Editore: Springer International Publishing, Springer Nature Switzerland Apr 2014, 2014
ISBN 10: 3319032208 ISBN 13: 9783319032207
Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
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Aggiungi al carrelloBuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection. It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD protection design is demonstrated with representative case studies which are analyzed with various numerical simulations and ESD testing. The overall methodology for IC-system ESD co-design is presented as a step-by-step procedure that involves both ESD testing and numerical simulations. 340 pp. Englisch.
Da: preigu, Osnabrück, Germania
EUR 102,20
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Aggiungi al carrelloBuch. Condizione: Neu. System Level ESD Protection | Vladislav Vashchenko (u. a.) | Buch | xviii | Englisch | 2014 | Springer | EAN 9783319032207 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu Print on Demand.
Lingua: Inglese
Editore: Springer, Springer Apr 2014, 2014
ISBN 10: 3319032208 ISBN 13: 9783319032207
Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germania
EUR 117,69
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Aggiungi al carrelloBuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection. It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD protection design is demonstrated with representative case studies which are analyzed with various numerical simulations and ESD testing. The overall methodology for IC-system ESD co-design is presented as a step-by-step procedure that involves both ESD testing and numerical simulations.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 340 pp. Englisch.
Da: Biblios, Frankfurt am main, HESSE, Germania
EUR 170,46
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Aggiungi al carrelloCondizione: New. PRINT ON DEMAND pp. 340.