9783838102870 - efficient and flexible cryptographic co-processor architecture: focussing on server application di laue, ralf (4 risultati)
Lingua: Inglese
Editore: Südwestdeutscher Verlag für Hochschulschriften, 2015
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Da: preigu, Osnabrück, Germaniapreigu
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EUR 69,90
EUR 70,00 spedizioneSpedito da Germania a U.S.A.Quantità: 5 disponibili
Taschenbuch. Condizione: Neu. Efficient and Flexible Cryptographic Co-Processor Architecture | Focussing on Server Application | Ralf Laue | Taschenbuch | 160 S. | Deutsch | 2015 | Südwestdeutscher Verlag für Hochschulschriften | EAN 9783838102870 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19…, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.
Lingua: Inglese
Editore: Südwestdeutscher Verlag für Hochschulschriften, 2015
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Da: moluna, Greven, Germaniamoluna
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
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Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. In todays networks security is becoming more and more important. Public Key Cryptography, which is a necessary building block for this, places a high workload on the server in client-server networks. A co-processor c…an be used to shoulder some of this workl.
Lingua: Inglese
Editore: Südwestdeutscher Verlag Für Hochschulschriften Jan 2009, 2009
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Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germaniabuchversandmimpf2000
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Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -In todays networks security is becoming more and more important. Public Key Cryptography, which is a necessary building block for this, places a high workload on the server in client-server networks. A co-processor can be used to shoul…der some of this workload. However, as the networks become increasingly heterongenous, the server must also be able to communicate with clients utilizing different cryptographic schemes. Thus, the two main design goals for such a co-processor are efficiency and flexibility. In context of server application, efficiency is measured as high throughput instead of low latency. Flexibility aims for the support of different cryptographic schemes and an easy expandability. This work proposes a generic co-processor architecture for RSA, Elliptic Curve Cryptography, and Pairing-Based Cryptography, which utilizes a combined HW/SW-design allowing high flexibility without sacrificing efficiency. Based on a new classification of parallelization possibilities, it exploits parallelization on all abstraction levels as long as this furthers throughput. The feasibility and usefulness of the architecture is verified by means of a prototype implementation.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 160 pp. Deutsch.
Lingua: Inglese
Editore: Südwestdeutscher Verlag Für Hochschulschriften AG Co. KG, 2008
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Da: AHA-BUCH GmbH, Einbeck, GermaniaAHA-BUCH GmbH
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 69,90
EUR 61,28 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - In todays networks security is becoming more and more important. Public Key Cryptography, which is a necessary building block for this, places a high workload on the server in client-server networks. A co-processor can be used to should…er some of this workload. However, as the networks become increasingly heterongenous, the server must also be able to communicate with clients utilizing different cryptographic schemes. Thus, the two main design goals for such a co-processor are efficiency and flexibility. In context of server application, efficiency is measured as high throughput instead of low latency. Flexibility aims for the support of different cryptographic schemes and an easy expandability. This work proposes a generic co-processor architecture for RSA, Elliptic Curve Cryptography, and Pairing-Based Cryptography, which utilizes a combined HW/SW-design allowing high flexibility without sacrificing efficiency. Based on a new classification of parallelization possibilities, it exploits parallelization on all abstraction levels as long as this furthers throughput. The feasibility and usefulness of the architecture is verified by means of a prototype implementation.
