Isbn: 9783846552438 - timing and signal integrity issues with vlsi interconnects: in sub-nanometer designs (9 risultati)

Condizione: New.

Paperback. Condizione: Brand New. 84 pages. 8.66x5.91x0.19 inches. In Stock.

Taschenbuch. Condizione: Neu. Timing and Signal Integrity Issues with VLSI Interconnects | In sub-nanometer designs | Debaprasad Das | Taschenbuch | 84 S. | Englisch | 2011 | LAP LAMBERT Academic Publishing | EAN 9783846552438 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.…

Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book discusses the timing and signal integrity issues with VLSI interconnects in sub-nanometer designs. Starting with the basics of interconnect equivalent circuit model it describes the RLC equivalent models of interconnects, their extraction methodologies, and circuit simulation for timing and signal integrity analysis. With enormous analysis results for different technology nodes the importance of on-chip inductive effects has been discussed. The sample simulation model along with the SPICE netlist for timing and signal integrity analysis has been provided in the appendix. The book will be useful to the teachers, students, and researchers who are involved in modeling and analyzing the interconnects in future generation VLSI technology nodes. The book comprises four chapters and one appendix. 84 pp. Englisch.…

Condizione: New. Print on Demand.

Condizione: New. PRINT ON DEMAND.

Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Das DebaprasadDebaprasad Das is Assistant Professor, Department of Electronics and Communication Engineering, Meghnad Saha Institute of Technology, Kolkata, India. He was a Senior Engineer at the ASIC product development centre, Texa.…

Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This book discusses the timing and signal integrity issues with VLSI interconnects in sub-nanometer designs. Starting with the basics of interconnect equivalent circuit model it describes the RLC equivalent models of interconnects, their extraction methodologies, and circuit simulation for timing and signal integrity analysis. With enormous analysis results for different technology nodes the importance of on-chip inductive effects has been discussed. The sample simulation model along with the SPICE netlist for timing and signal integrity analysis has been provided in the appendix. The book will be useful to the teachers, students, and researchers who are involved in modeling and analyzing the interconnects in future generation VLSI technology nodes. The book comprises four chapters and one appendix.…

Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book discusses the timing and signal integrity issues with VLSI interconnects in sub-nanometer designs. Starting with the basics of interconnect equivalent circuit model it describes the RLC equivalent models of interconnects, their extraction methodologies, and circuit simulation for timing and signal integrity analysis. With enormous analysis results for different technology nodes the importance of on-chip inductive effects has been discussed. The sample simulation model along with the SPICE netlist for timing and signal integrity analysis has been provided in the appendix. The book will be useful to the teachers, students, and researchers who are involved in modeling and analyzing the interconnects in future generation VLSI technology nodes. The book comprises four chapters and one appendix.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 84 pp. Englisch.…