ISBN: 9783846554630 - approaches for hardware fault mitigation in multicore processors: resilient systems with unreliable devices (10 risultati)

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Condizione: New.

Paperback. Condizione: Brand New. 192 pages. 8.66x5.91x0.44 inches. In Stock.

Paperback. Condizione: Brand New. 192 pages. 8.66x5.91x0.44 inches. In Stock.

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Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This thesis addresses one of the fundamental challenges emerging in microprocessor design, namely hardware reliability and resilience. Since inception in the 70's, microprocessors have primarily benefited from technological advancements in semiconductors fabrication allowing for an exponential increase in computing capability of chips by shrinking transistors sizes. Unfortunately, forecasts indicate that further shrinking in size will be accompanied by variability in transistor performance and reliability. This thesis proposes novel designs and enhancements to provide hardware reliability for parallel workloads. In particular, it is provided noteworthy improvements in Redundant Multi Threading (RMT) fault-tolerant approaches, as well as novel Expected Miss Ratio (EMR) model to determine the impact of hard faults on cache memories. 192 pp. Englisch.…

Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This thesis addresses one of the fundamental challenges emerging in microprocessor design, namely hardware reliability and resilience. Since inception in the 70's, microprocessors have primarily benefited from technological advancements in semiconductors fabrication allowing for an exponential increase in computing capability of chips by shrinking transistors sizes. Unfortunately, forecasts indicate that further shrinking in size will be accompanied by variability in transistor performance and reliability. This thesis proposes novel designs and enhancements to provide hardware reliability for parallel workloads. In particular, it is provided noteworthy improvements in Redundant Multi Threading (RMT) fault-tolerant approaches, as well as novel Expected Miss Ratio (EMR) model to determine the impact of hard faults on cache memories.…

Condizione: New. Print on Demand.

Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This thesis addresses one of the fundamental challenges emerging in microprocessor design, namely hardware reliability and resilience. Since inception in the 70's, microprocessors have primarily benefited from technological advancements in semiconductors fabrication allowing for an exponential increase in computing capability of chips by shrinking transistors sizes. Unfortunately, forecasts indicate that further shrinking in size will be accompanied by variability in transistor performance and reliability. This thesis proposes novel designs and enhancements to provide hardware reliability for parallel workloads. In particular, it is provided noteworthy improvements in Redundant Multi Threading (RMT) fault-tolerant approaches, as well as novel Expected Miss Ratio (EMR) model to determine the impact of hard faults on cache memories.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 192 pp. Englisch.…

Condizione: New. PRINT ON DEMAND.