9783846554630 - approaches for hardware fault mitigation in multicore processors: resilient systems with unreliable devices di sánchez, daniel (10 risultati)
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Da: moluna, Greven, Germaniamoluna
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Condizione: New.
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Da: Books Puddle, New York, NY, U.S.A.Books Puddle
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Da: preigu, Osnabrück, Germaniapreigu
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Taschenbuch. Condizione: Neu. Approaches for Hardware Fault Mitigation in Multicore Processors | Resilient systems with unreliable devices | Daniel Sánchez | Taschenbuch | 192 S. | Englisch | 2011 | LAP LAMBERT Academic Publishing | EAN 9783846554630 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr.… 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.
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Da: Revaluation Books, Exeter, Regno UnitoRevaluation Books
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Paperback. Condizione: Brand New. 192 pages. 8.66x5.91x0.44 inches. In Stock.
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Da: Mispah books, Redhill, SURRE, Regno UnitoMispah books
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EUR 221,50
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paperback. Condizione: New. New .Ships From Multiple Locations. book.
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Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermaniaBuchWeltWeit Ludwig Meier e.K.
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Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This thesis addresses one of the fundamental challenges emerging in microprocessor design, namely hardware reliability and resilience. Since inception in the 70's, microprocessors have primarily benefited from technological advance…ments in semiconductors fabrication allowing for an exponential increase in computing capability of chips by shrinking transistors sizes. Unfortunately, forecasts indicate that further shrinking in size will be accompanied by variability in transistor performance and reliability. This thesis proposes novel designs and enhancements to provide hardware reliability for parallel workloads. In particular, it is provided noteworthy improvements in Redundant Multi Threading (RMT) fault-tolerant approaches, as well as novel Expected Miss Ratio (EMR) model to determine the impact of hard faults on cache memories. 192 pp. Englisch.
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Da: Majestic Books, Hounslow, Regno UnitoMajestic Books
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EUR 106,28
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Da: Biblios, frankfurt am main, HESSE, GermaniaBiblios
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EUR 110,17
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Condizione: New. PRINT ON DEMAND.
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Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germaniabuchversandmimpf2000
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EUR 68,00
EUR 60,00 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This thesis addresses one of the fundamental challenges emerging in microprocessor design, namely hardware reliability and resilience. Since inception in the 70's, microprocessors have primarily benefited from technological advancement…s in semiconductors fabrication allowing for an exponential increase in computing capability of chips by shrinking transistors sizes. Unfortunately, forecasts indicate that further shrinking in size will be accompanied by variability in transistor performance and reliability. This thesis proposes novel designs and enhancements to provide hardware reliability for parallel workloads. In particular, it is provided noteworthy improvements in Redundant Multi Threading (RMT) fault-tolerant approaches, as well as novel Expected Miss Ratio (EMR) model to determine the impact of hard faults on cache memories.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 192 pp. Englisch.
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Da: AHA-BUCH GmbH, Einbeck, GermaniaAHA-BUCH GmbH
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EUR 68,00
EUR 61,52 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This thesis addresses one of the fundamental challenges emerging in microprocessor design, namely hardware reliability and resilience. Since inception in the 70's, microprocessors have primarily benefited from technological advancements… in semiconductors fabrication allowing for an exponential increase in computing capability of chips by shrinking transistors sizes. Unfortunately, forecasts indicate that further shrinking in size will be accompanied by variability in transistor performance and reliability. This thesis proposes novel designs and enhancements to provide hardware reliability for parallel workloads. In particular, it is provided noteworthy improvements in Redundant Multi Threading (RMT) fault-tolerant approaches, as well as novel Expected Miss Ratio (EMR) model to determine the impact of hard faults on cache memories.
