Isbn: 9783847310303 - design and analysis of high performance full adder cell: a low power approach (5 risultati)

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Taschenbuch. Condizione: Neu. Design and Analysis of High Performance Full Adder Cell | A Low Power Approach | Deepa Sinha (u. a.) | Taschenbuch | 76 S. | Englisch | 2011 | LAP LAMBERT Academic Publishing | EAN 9783847310303 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.…

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Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Full adder is an essential component for designing all types of processors viz. digital signal processors (DSP), microprocessors etc. In most of the digital systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is of prime concern. This book presents the general methodology to modify performance of full adder by adding an extra transistor to the node causing loss. The introduced design of full adder cell remarkably reduces power consumption hence PDP, improves noise immunity and temperature sustainability in comparison to the conventional design. All simulations are performed on 45nm and 90nm standard models on Tanned EDA tool version 12.6. This book, therefore, provides a new metric of implementing high performance technology independent full adder circuit and the Ripple Carry Adder as its application. The analysis should help shed some light on the new and exciting approach for achieving low power and high throughput adder cell and should be especially useful to post graduate students and research scholars in VLSI circuit design field. 76 pp. Englisch.…

Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Full adder is an essential component for designing all types of processors viz. digital signal processors (DSP), microprocessors etc. In most of the digital systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is of prime concern. This book presents the general methodology to modify performance of full adder by adding an extra transistor to the node causing loss. The introduced design of full adder cell remarkably reduces power consumption hence PDP, improves noise immunity and temperature sustainability in comparison to the conventional design. All simulations are performed on 45nm and 90nm standard models on Tanned EDA tool version 12.6. This book, therefore, provides a new metric of implementing high performance technology independent full adder circuit and the Ripple Carry Adder as its application. The analysis should help shed some light on the new and exciting approach for achieving low power and high throughput adder cell and should be especially useful to post graduate students and research scholars in VLSI circuit design field.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 76 pp. Englisch.…