9786139845651 - low power cmos approximate voting architecture for reliable computing di sundaram, kalaiselvi; krishnasamy natarajan, vijeyakumar; natarajan, saravanakumar (5 risultati)
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Da: preigu, Osnabrück, Germaniapreigu
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Taschenbuch. Condizione: Neu. Low Power CMOS Approximate Voting Architecture for Reliable Computing | Kalaiselvi Sundaram (u. a.) | Taschenbuch | 56 S. | Englisch | 2018 | LAP LAMBERT Academic Publishing | EAN 9786139845651 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bo…d[dot]de | Anbieter: preigu.
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Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermaniaBuchWeltWeit Ludwig Meier e.K.
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Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Soft errors have a predominant role in the design of integrated electronic circuits. Modular Redundancy is a technique used to suppress the effects caused by soft error. In conventional Triple Modular Redundancy scheme, voter gener…ates error if majority cannot be detected. Introducing approximations in the conventional schemes reduces the error probability. The book presents the design of approximate scheme for alleviating the soft error by combining Inexact Double Modular Redundancy and Approximate Triple Modular Redundancy. The Approximate TMR module overcomes this problem by mediating the output instead of generating error. The scheme is designed using Cadence EDA tool with 180nm technology. Parameter analysis revealed power of the approximate design is being reduced by 49.11% from the existing design. 56 pp. Englisch.
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Low Power CMOS Approximate Voting Architecture for Reliable Computing
Kalaiselvi Sundaram|Vijeyakumar Krishnasamy Natarajan|Saravanakumar Natarajan
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Da: moluna, Greven, Germaniamoluna
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Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Sundaram KalaiselviMs.S.Kalaiselvi completed her Under graduation in ECE in the year 2011 and Masters in Engineering in Applied Electronics under Anna University, Chennai. She has published 5 journals…and presented papers in more t.
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Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germaniabuchversandmimpf2000
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Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Soft errors have a predominant role in the design of integrated electronic circuits. Modular Redundancy is a technique used to suppress the effects caused by soft error. In conventional Triple Modular Redundancy scheme, voter generates… error if majority cannot be detected. Introducing approximations in the conventional schemes reduces the error probability. The book presents the design of approximate scheme for alleviating the soft error by combining Inexact Double Modular Redundancy and Approximate Triple Modular Redundancy. The Approximate TMR module overcomes this problem by mediating the output instead of generating error. The scheme is designed using Cadence EDA tool with 180nm technology. Parameter analysis revealed power of the approximate design is being reduced by 49.11% from the existing design.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 56 pp. Englisch.
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Da: AHA-BUCH GmbH, Einbeck, GermaniaAHA-BUCH GmbH
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 37,20
EUR 60,51 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Soft errors have a predominant role in the design of integrated electronic circuits. Modular Redundancy is a technique used to suppress the effects caused by soft error. In conventional Triple Modular Redundancy scheme, voter generates…error if majority cannot be detected. Introducing approximations in the conventional schemes reduces the error probability. The book presents the design of approximate scheme for alleviating the soft error by combining Inexact Double Modular Redundancy and Approximate Triple Modular Redundancy. The Approximate TMR module overcomes this problem by mediating the output instead of generating error. The scheme is designed using Cadence EDA tool with 180nm technology. Parameter analysis revealed power of the approximate design is being reduced by 49.11% from the existing design.
