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Aggiungi al carrelloCondizione: New. In.
Condizione: New. pp. 196.
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Aggiungi al carrelloPaperback. Condizione: Brand New. reprint edition. 192 pages. 9.40x6.20x0.60 inches. In Stock.
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Aggiungi al carrelloTaschenbuch. Condizione: Neu. VLSI Planarization | Methods, Models, Implementation | V Z Feinberg (u. a.) | Taschenbuch | Einband - flex.(Paperback) | Englisch | 2012 | Springer | EAN 9789401064217 | Verantwortliche Person für die EU: Springer Netherlands, Haberstr. 7, 69126 Heidelberg, buchhandel-buch[at]springer[dot]com | Anbieter: preigu.
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Aggiungi al carrelloTaschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - At the beginning we would like to introduce a refinement. The term 'VLSI planarization' means planarization of a circuit of VLSI, Le. the embedding of a VLSI circuit in the plane by different criteria such as the minimum number of connectors, the minimum total length of connectors, the minimum number of over-the-element routes, etc. A connector is designed to connect the broken sections of a net. It can be implemented in different ways depending on the technology. Connectors for a bipolar VLSI are implemented by diffused tun nels, for instance. By over-the-element route we shall mean a connection which intersects the enclosing rectangle of an element (or a cell). The possibility of the construction such connections during circuit planarization is reflected in element models and can be ensured, for example, by the availability of areas within the rectangles where connections may be routed. VLSI planarization is one of the basic stages (others will be discussed below) of the so called topological (in the mathematical sense) approach to VLSI design. This approach does not lie in the direction of the classical approach to automation of VLSI layout design. In the classical approach to computer aided design the placement and routing problems are solved successively. The topological approach, in contrast, allows one to solve both problems at the same time. This is achieved by constructing a planar embedding of a circuit and obtaining the proper VLSI layout on the basis of it.
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Aggiungi al carrelloCondizione: New. At the beginning we would like to introduce a refinement. The term VLSI planarization means planarization of a circuit of VLSI, Le. the embedding of a VLSI circuit in the plane by different criteria such as the minimum number of connectors, the minimum to.
Lingua: Inglese
Editore: Springer, Springer Okt 2012, 2012
ISBN 10: 9401064210 ISBN 13: 9789401064217
Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
EUR 106,99
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Aggiungi al carrelloTaschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -At the beginning we would like to introduce a refinement. The term 'VLSI planarization' means planarization of a circuit of VLSI, Le. the embedding of a VLSI circuit in the plane by different criteria such as the minimum number of connectors, the minimum total length of connectors, the minimum number of over-the-element routes, etc. A connector is designed to connect the broken sections of a net. It can be implemented in different ways depending on the technology. Connectors for a bipolar VLSI are implemented by diffused tun nels, for instance. By over-the-element route we shall mean a connection which intersects the enclosing rectangle of an element (or a cell). The possibility of the construction such connections during circuit planarization is reflected in element models and can be ensured, for example, by the availability of areas within the rectangles where connections may be routed. VLSI planarization is one of the basic stages (others will be discussed below) of the so called topological (in the mathematical sense) approach to VLSI design. This approach does not lie in the direction of the classical approach to automation of VLSI layout design. In the classical approach to computer aided design the placement and routing problems are solved successively. The topological approach, in contrast, allows one to solve both problems at the same time. This is achieved by constructing a planar embedding of a circuit and obtaining the proper VLSI layout on the basis of it. 196 pp. Englisch.
Da: Majestic Books, Hounslow, Regno Unito
EUR 145,39
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Aggiungi al carrelloCondizione: New. Print on Demand pp. 196 49:B&W 6.14 x 9.21 in or 234 x 156 mm (Royal 8vo) Perfect Bound on White w/Gloss Lam.
Da: Biblios, Frankfurt am main, HESSE, Germania
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Aggiungi al carrelloCondizione: New. PRINT ON DEMAND pp. 196.