art analog layout 2nd di hastings alan (3 risultati)

Soft cover. Condizione: New. Condizione sovraccoperta: New. International Edition. **INTERNATIONAL EDITION** Read carefully before purchase: This book is the international edition in mint condition with the different ISBN and book cover design, the major content is printed in full English as same as the original North American edition. The book printed in black and white, generally send in twenty-four hours after the order confirmed. All shipments go through via USPS/UPS/DHL with tracking numbers. Great professional textbook selling experience and expedite shipping service.

Soft cover. Condizione: New. Condizione sovraccoperta: New. International Edition. ***INTERNATIONAL EDITION*** Read carefully before purchase: This book is the international edition in mint condition with the different ISBN and book cover design, the major content is printed in full English as same as the original North American edition. The book printed in black and white, generally send in twenty-four hours after the order confirmed. All shipments contain tracking numbers. Great professional textbook selling experience and expedite shipping service. Sewn binding. Cloth over boards. 672 p. Audience: General/trade.

paperback. Condizione: New. Ship out in 2 business day, And Fast shipping, Free Tracking number will be provided after the shipment.Paperback. Pub Date: 2013 Pages: 664 Language: English Publisher: Publishing House of Electronics Industry foreign electronic communications textbook series: Art of analog circuit layout (2nd Edition) (English version) practical and authoritative view comprehensive discussion of the various issues involved in the analog IC layout design and the latest research. The book describes the content of the semiconductor device physics and technology. failure mechanisms; based on three basic process used in analog integrated circuit design: standard bipolar process. the polysilicon gate CMOS and analog BiCMOS process. focusing on the design of passive components matching problems. the design and application of diode design. bipolar transistors and field-effect transistor. and the contents of some of the areas of expertise. including device consolidation. protection ring. pad production. single connection. ESD structures. etc.; Finally The layout of the chip layout wiring knowledge. Contents: Chapter 1 Device Physics 1.1 Semiconductor 1.2 PN junction 1.3 bipolar transistor 1.4 MOS transistor 1.5 JFET transistor 1.6 Summary 1.7 Exercises Chapter 2 semiconductor manufacturing 2.1 silicon manufacturing 2.2 lithography the 2.3 oxide growth and removal of 2.4 diffusion and ion the injected of 2.5 silicon deposition and etching 2.6 metalization assembled 2.8 Summary 2.9 Exercises Chapter 3. the typical process 3.1 standard bipolar process 3.2 polysilicon gate CMOS process 3.3 analog BiCMOS3.4 Summary 3.5 Exercises Chapter 4 failure mechanisms 4.1 electrical overstress 4.2 2.7 defiled parasitic effects of the on 4.3 surface effect 4.4 4.5 Summary 4.6 Exercises Chapter 5 resistor 5.1 resistivity and sheet resistance (sheet resistance) 5.2 resistor layout 5.3 Resistance variation the 5.4 resistor parasitics 5.5 resistor type comparison 5.6 adjusts resistor 5.7 Summary 7.4 Summary 7.5 Exercises. 5.8 exercises Chapter 6 of capacitance and inductance 6.1 Capacitance 6.2 inductors 6.3 Summary 6.4 Exercises Chapter 7. resistor and capacitor matching 7.1 mismatch measuring 7.2 mismatch causes 7.3 device matching rules Chapter 8 bipolar transistor 8.1 8.4 Summary 8.5 8.2 Standard of the working principle of the bipolar transistor the bipolar small signal transistors 8.3 CMOS and BiCMOS processes small signal bipolar transistor exercises power bipolar transistor in Chapter 9 of the bipolar transistor application 9.1 9.2 bipolar transistor 9.4 Summary 9.5 Exercises Chapter 10 diode the 10.1 standard bipolar process Diode 10.2 CMOS and BiCMOS processes diode 10.3 matched diode 10.4 Summary 10.5 Exercises Chapter 11 11.1 MOS field effect transistor transistor works 11.2 constructor matching 9.3 bipolar transistor matching design rules Application of CMOS transistors 11.3 floating gate transistor 11.4 JFET transistor 11.5 Summary 11.6 Exercises Chapter 12 MOS transistors 12.1 extended power MOS transistors of the voltage transistors 12.2 12.3 MOS transistor matching 12.4 MOS transistor matching rule 12.5 Summary 12.6 Exercises Chapter 13 thematic 13.1 merge Construction of guard ring device 13.2 13.3 single-layer interconnect 13.4 13.6 Problem Chapter 14 of the pad ring 13.5 ESD structure assembly die die 14.2 14.1 planning layout 14.3 Summary 14.5 Exercises top-level interconnect 14.4 Abbreviation Glossary Appendix A Appendix B cubic crystal m Le index Appendix C territory rule instance Appendix D mathematical derivation in Appendix E of the provenance of the layout editing softwareFour Satisfaction guaranteed,or money back.