Editore: Edizioni Accademiche Italiane, 2014
ISBN 10: 3639487532 ISBN 13: 9783639487534
Lingua: Inglese
Da: moluna, Greven, Germania
EUR 32,02
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Aggiungi al carrelloCondizione: New.
Editore: Edizioni Accademiche Italiane Feb 2014, 2014
ISBN 10: 3639487532 ISBN 13: 9783639487534
Lingua: Inglese
Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germania
EUR 36,90
Convertire valutaQuantità: 2 disponibili
Aggiungi al carrelloTaschenbuch. Condizione: Neu. Neuware -Currently, multiprocessors and multi-cores are very complex and heterogeneous systems with parallelism exploited at processes level. The trend seems that the number of cores per chip is expected to double every two years - the idea is to substitute few complex and power-consuming CPUs with many smaller and simpler CPUs that can deliver better performance per watt. Such architectures can be exploited efficiently pro- vided that applications are able to do it. In order to do so a methodological and structured approach is needed to keep low the complexity of the resolution. On one hand, structured parallel programming is used in order to create parallel applications independent of the underline architecture. On the other hand, a cost model in association with an abstract architecture is needed from the performance prediction point of view. This book is a contribution on that approach enhancing the cost models for shared memory architectures and its accuracy with particular care to parallel application constraints.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 152 pp. Englisch.
Editore: Edizioni Accademiche Italiane Feb 2014, 2014
ISBN 10: 3639487532 ISBN 13: 9783639487534
Lingua: Inglese
Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
EUR 36,90
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Aggiungi al carrelloTaschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Currently, multiprocessors and multi-cores are very complex and heterogeneous systems with parallelism exploited at processes level. The trend seems that the number of cores per chip is expected to double every two years - the idea is to substitute few complex and power-consuming CPUs with many smaller and simpler CPUs that can deliver better performance per watt. Such architectures can be exploited efficiently pro- vided that applications are able to do it. In order to do so a methodological and structured approach is needed to keep low the complexity of the resolution. On one hand, structured parallel programming is used in order to create parallel applications independent of the underline architecture. On the other hand, a cost model in association with an abstract architecture is needed from the performance prediction point of view. This book is a contribution on that approach enhancing the cost models for shared memory architectures and its accuracy with particular care to parallel application constraints. 152 pp. Englisch.
Da: AHA-BUCH GmbH, Einbeck, Germania
EUR 36,90
Convertire valutaQuantità: 1 disponibili
Aggiungi al carrelloTaschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Currently, multiprocessors and multi-cores are very complex and heterogeneous systems with parallelism exploited at processes level. The trend seems that the number of cores per chip is expected to double every two years - the idea is to substitute few complex and power-consuming CPUs with many smaller and simpler CPUs that can deliver better performance per watt. Such architectures can be exploited efficiently pro- vided that applications are able to do it. In order to do so a methodological and structured approach is needed to keep low the complexity of the resolution. On one hand, structured parallel programming is used in order to create parallel applications independent of the underline architecture. On the other hand, a cost model in association with an abstract architecture is needed from the performance prediction point of view. This book is a contribution on that approach enhancing the cost models for shared memory architectures and its accuracy with particular care to parallel application constraints.