performance evaluation high speed (7 risultati)

Paperback. Condizione: Brand New. 188 pages. 8.66x5.91x0.43 inches. In Stock.

Condizione: New. pp. 478.

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Hardcover. Condizione: Like New. Like New. book.

paperback. Condizione: New. Language:Chinese.Paperback.Pub Date:2024-01 Pages:424 Publisher:Science Press:This book mainly introduces the relevant research results and practical engineering application experience of the performance degradation mechanism and quality assessment method of non-operated track of high-speed railway. Focusing on the key problems existing in the service of non-operated track. a simulation calculation model of non-operated track structure considering the complex constitutive relationship of mate.

Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This book summarizes the study on signaling design in ultra-wideband (UWB) system wireless communication systems. UWB signaling design can be effectively manipulated for the purposes of performance improvement and interference mitigation. Timing jitter, as a critical issue in UWB signaling design, is also investigated to assess its impact to system performance. Chapter 1 describes the research background, and the motivation that becomes the catalyst to the completion of this study. Chapter 2 provides an overall introduction to UWB systems, with specific emphasis on direct sequence (DS) and DS multiband (MB) approaches. Chapter 3 deals with signaling design in varying low chip duty factor (DF), a unique parameter in UWB system. Chapter 4 proposes two interference mitigation techniques developed by manipulating signaling design in DS and DS-MB UWB system. Chapter 5 highlights and mitigates the impact of timing jitter in UWB signaling design.

Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The remarkable increase in transistor densities in modern VLSI systems has direct to a surge in power and energy dissipation to levels not seen before. This tendency will continue to produce as more transistors are packed into the same area. Therefore, power and energy-aware design flows are becoming trendy in both ends of the design space, high-performance and portable applications. In this study, the power and energy reduction techniques at the architecture, circuit, and device levels are presented. With the intention of diminishing power, we proposed a novel method for Conventional Array Multiplier. In the proposed design, final adder RCA is removed and the generated carry bits from the partial products are fed to the input of a full adder cell whose one of the input is zero. We applied final adder RCA removal method at the final addition stage of Column Bypassing Multiplier and Modified Booth Encoder Multiplier for low power applications. The proposed MBEM encoder is designed with only one XOR with two inputs and two outputs. Between two outputs, one is taken at before of an inverter, the function is XNOR. The second is taken at after the inverter for XOR function.