Articoli correlati a Yield Simulation for Integrated Circuits: 33
Sinossi
In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself.
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Contenuti
1. Introduction.- 2. Background.- 3. Defect Models.- 4. Defect Statistics.- 5. Fault Analysis.- 6. VLASIC Implementation.- 7. Redundancy Analysis System.- 8. Fabrication Data.- 9. Conclusions and Current Research.- References.
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- EditoreKluwer Academic Pub
- Data di pubblicazione1987
- ISBN 10 0898382440
- ISBN 13 9780898382440
- RilegaturaCopertina rigida
- LinguaInglese
- Numero di pagine226
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Yield Simulation for Integrated Circuits (The Springer International Series in Engineering and Computer Science, 33)
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Yield Simulation for Integrated Circuits (The Kluwer International Series in Engineering and Computer Science)
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Kluwer Academic Publishers, Lancaster, United Kingdom, 1987
ISBN 10: 0898382440
ISBN 13: 9780898382440
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1987 HC Yield Simulation for Integrated Circuits (The Springer International Series in Engineering and Computer Science, 33)
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Buch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself. 226 pp. Englisch. Codice articolo 9780898382440
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Yield Simulation for Integrated Circuits (The Springer International Series in Engineering and Computer Science, 33)
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Yield Simulation for Integrated Circuits
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Buch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and redundancy programming. The fabrication technology did not yet exist, so I was unable to experimentally verify the benefits of redundancy. When the technology did become available, it would be too late in the development schedule to spend time running test chips. The yield analysis had to be done analytically or by simulation. Analytic yield analysis techniques did not offer sufficient accuracy for dealing with complex structures. The simulation techniques then available were very labor-intensive and seemed more suitable for redundant memories and other very regular structures [Stapper 80J. I wanted a simulator that would allow me to evaluate the yield of arbitrary redundant layouts, hence I termed such a simulator a layout or yield simulator. Since I was unable to convince anyone to build such a simulator for me, I embarked on the research myself. Codice articolo 9780898382440
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Yield Simulation for Integrated Circuits (The Springer International Series in Engineering and Computer Science, 33)
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