Digital System Test and Testable Design: Using HDL Models and Architectures - Brossura

Navabi, Zainalabedin

Brossura

ISBN 10: 1489979271 ISBN 13: 9781489979278

Casa editrice: Springer, 2016

Riassunto

Describes test methods in Verilog and PLI, which makes the methods more understandable and the gates possible to simulate Simulation of gate models allows fault simulation and test generation, while Verilog testbenches inject faults, evaluate fault coverage and apply new test patterns Describes DFT, compression, decompression, and BIST techniques in Verilog, which makes the hardware of the architectures easier to understand and allows simulation and evaluation of the testability methods

Su questo libro

Informazioni sull?autore

About the AuthorDr. Zainalabedin Navabi is a professor of electrical and computer engineering at Worcester Polytechnic Institute. Dr. Navabi is the author of several textbooks and computer based trainings on VHDL, Verilog and related tools and environments. Dr. Navabis involvement with hardware description languages begins in 1976, when he started the development of a register-transfer level simulator for one of the very first HDLs. In 1981 he completed the development of a synthesis tool that generated MOS layout from an RTL description. Since 1981, Dr. Navabi has been involved in the design, definition and implementation of Hardware Description Languages. He has written numerous papers on the application of HDLs in simulation, synthesis and test of digital systems. He started one of the first full HDL courses at Northeastern University in 1990. Since then he has conducted many short courses and tutorials on this subject in the United States and abroad. In addition to being a professor, he is also a consultant to CAE companies. Dr. Navabi received his M.S. and Ph.D. from the University of Arizona in 1978 and 1891, and his B.S. from the University of Texas at Austin in 1975. He is a senior member of IEEE, a member of IEEE Computer Society, member of ASEE, and ACM.

Dalla quarta di copertina

Digital System Test and Testable Design: Using HDL Models and Architectures by: Zainalabedin Navabi This book is about digital system test and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms.Extensive use of Verilog and Verilog PLI for test applications is what distinguishesthis book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware / software environment facilitates description of complex test programs and test strategies. Combines design and testDescribes test methods in Verilog and PLI, which makes the methods more understandable and the gates possible to simulateSimulation of gate models allows fault simulation and test generation, while Verilog testbenches inject faults, evaluate fault coverage and apply new test patternsDescribes DFT, compression, decompression, and BIST techniques in Verilog, which makes the hardware of the architectures easier to understand and allows simulation and evaluation of the testability methodsVirtual testers (Verilog testbenches) play the role of ATEs for driving scan tests and examining the circuit under testVerilog descriptions of scan designs and BIST architectures are available that can be used in actual designsPLI test utilities developed in-text are available for downloadIntroductory Video for Verilog basics, software developed in-text, and PLI basics available for downloadPowerpoint slides available for each chapter

Dettagli dell?edizione

• Editore: Springer
• Data di pubblicazione: 2016
• Lingua: Inglese
• ISBN 10: 1489979271
• ISBN 13: 9781489979278
• Rilegatura: Copertina flessibile
• Numero di pagine: 460
• Contatto del produttore: Springer Nature Customer Service Center GmbH; ProductSafety@springernature.com