A Pipelined Multi-Core Machine with Operating System Support: Hardware Implementation and Correctness Proof: 9999 - Brossura

Lutsyk, Petro; Oberhauser, Jonas; Paul, Wolfgang J.

Brossura

ISBN 10: 3030432424 ISBN 13: 9783030432423

Casa editrice: Springer, 2020

Riassunto

<div><p>This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.</p><p>It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:<br></p><p>• MIPS instruction set architecture (ISA) for application and for system programming<br></p><p>• cache coherent memory system</p><p>• store buffers in front of the data caches</p><p>• interrupts and exceptions</p>• memory management units (MMUs)<p></p><p>• pipelined processors: the classical five-stage pipeline is extended by two pipeline</p><p>stages for address translation</p><p>• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)</p><p>• I/O-interrupt controller and a disk</p><p>&nbsp;</p></div>

Su questo libro

Dalla quarta di copertina

<div><p>This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.</p><p>It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:</p><p>• MIPS instruction set architecture (ISA) for application and for system programming</p><p>• cache coherent memory system</p><p>• store buffers in front of the data caches</p><p>• interrupts and exceptions</p><p>• memory management units (MMUs)</p><p>• pipelined processors: the classical five-stage pipeline is extended by two pipeline</p><p>stages for address translation</p><p>• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)</p><p><p>• I/O-interrupt controller and a disk</p></p><br><p><br></p><p>&nbsp;</p></div>

Dettagli dell'edizione

• Editore: Springer
• Data di pubblicazione: 2020
• Lingua: Inglese
• ISBN 10: 3030432424
• ISBN 13: 9783030432423
• Rilegatura: Copertina flessibile
• Numero edizione: 1
• Numero di pagine: 644
• Contatto del produttore: Springer Nature Customer Service Center GmbH; ProductSafety@springernature.com; ; Europaplatz 3,69115 Heidelberg, Germany; Heidelberg; 69115; Germania