Implementation of a Binary Floating Point Fused Multiply-Add Unit - Brossura

Abdel Aziz Ibrahim, Walaa; Aly Fahmy, Hossam; Hussien Khalil, Ahmed

 
9783846546215: Implementation of a Binary Floating Point Fused Multiply-Add Unit

Sinossi

The fused multiply add (FMA) operation is very important in many scientific and engineering applications. It is a key feature of the floating-point unit (FPU), which greatly increases the floating-point performance and accuracy.Many approaches are developed on floating-point fused multiply add unit to decrease its latency.two of these approaches are implemented in the Verilog hardware description language. ModelSim10.0c is a used to compile Verilog codes and to simulate them.

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L'autore

Walaa Abdel Aziz,Assistant Lecturer,Faculty of Engineering,Modern Academy for Engineering and Technology,Has awarded M.sc. from Electronics and Electrical Communication Department,Faculty of Engineering, Cairo University,March 2011.

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