VLSI Planarization: Methods, Models, Implementation: 399 - Brossura

Feinberg, V.Z.; Levin, A.G.; Rabinovich, E.B.

Brossura

ISBN 10: 9401064210 ISBN 13: 9789401064217

Casa editrice: Springer, 2012

Riassunto

At the beginning we would like to introduce a refinement. The term 'VLSI planarization' means planarization of a circuit of VLSI, Le. the embedding of a VLSI circuit in the plane by different criteria such as the minimum number of connectors, the minimum total length of connectors, the minimum number of over-the-element routes, etc. A connector is designed to connect the broken sections of a net. It can be implemented in different ways depending on the technology. Connectors for a bipolar VLSI are implemented by diffused tun­ nels, for instance. By over-the-element route we shall mean a connection which intersects the enclosing rectangle of an element (or a cell). The possibility of the construction such connections during circuit planarization is reflected in element models and can be ensured, for example, by the availability of areas within the rectangles where connections may be routed. VLSI planarization is one of the basic stages (others will be discussed below) of the so called topological (in the mathematical sense) approach to VLSI design. This approach does not lie in the direction of the classical approach to automation of VLSI layout design. In the classical approach to computer­ aided design the placement and routing problems are solved successively. The topological approach, in contrast, allows one to solve both problems at the same time. This is achieved by constructing a planar embedding of a circuit and obtaining the proper VLSI layout on the basis of it.

Su questo libro

Recensione

`Altogether, the book is very well written and a good piece of work. All the notions are clearly defined and the proofs are presented in detail. Many pictures illustrate the subjects discussed and help to make things clear and understandable.'
Mathematical Reviews, 98m

Contenuti

Introduction. 1. Discrete Mathematics Fundamentals. 2. Graph Planarization. 3. Hypergraph Planarization. 4. Mathematical Models for VLSI Planarization Problem. 5. Extracting a Maximum Planar VLSI Part. 6. Constructing Nonplanar Connections. 7. Planarization System Structure. References. Index.

Dettagli dell'edizione

• Editore: Springer
• Data di pubblicazione: 2012
• Lingua: Inglese
• ISBN 10: 9401064210
• ISBN 13: 9789401064217
• Rilegatura: Copertina flessibile
• Numero di pagine: 196
• Contatto del produttore: non disponibile
• Persona responsabile: Springer Nature Customer Service Center GmbH; ProductSafety@springernature.com; ; Europaplatz 3,69115 Heidelberg, Germany; Heidelberg; 69115; Germania