Planar Processing Primer is based on lecture notes for a silicon planar process ing lecture/lab course offered at the University of Illinois-UC for over fifteen years. Directed primarily to electrical engineering upperclassmen and graduate students, the material also has been used successfully by graduate students in physics and ceramic and metallurgical engineering. It is suitable for self-study by engineers trained in other disciplines who are beginning work in the semiconductor fields, and it can make circuit design engineers aware of the processing limitations under which they must work. The text describes and explains, at an introductory level, the principal processing steps used to convert raw silicon into a semiconductor device or integrated circuit. First-order models are used for theoretical treatments (e.g., of diffusion and ion implantation), with reference made to more advanced treatments, to computer programs such as SUPREM that include higher order effects, and to interactions among sequential processes. In Chapters 8, 9, and to, the application of silicon processes to compound semiconductors is discussed briefly. Over the past several years, the size of transistors has decreased markedly, allowing more transistors per chip unit area, and chip size has increased.
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1. Planar Processing and Basic Devices.- 1.1 Basic Devices.- 1.2 Device Isolation.- 1.3 Interconnects.- 1.4 Basic Processes.- 1.5 Insulating Layer Fabrication.- 1.6 Silicon Layer Deposition.- 1.7 Selectively Doping Silicon.- 1.8 Pattern Delimitation; Lithography.- 1.9 Summary.- 2. Wafers.- 2.1 Crystallographic Considerations.- 2.2 Mono- versus Polycrystals.- 2.3 Structure, Planes, and Directions.- 2.4 Principal Plane Properties.- 2.5 Crystal Structure Implications.- 2.6 Scribing Considerations.- 2.7 Doping Considerations.- 2.8 Polysilicon Preparation.- 2.9 Single-Crystal Growth.- 2.10 Czochralski Method.- 2.11 Float Zone Method.- 2.12 Wafer Preparation.- 3. Wafer Measurements.- 3.1 Type Determination.- 3.2 Resistivity and Doping Measurements.- 3.3 Van der Pauw Measurement.- 3.4 Four Point Probe (FPP).- 3.5 Thickness Correction Factors.- 3.6 Diffused or Implanted Layers.- 3.7 Size Correction Factors.- 3.8 Sheet Resistance (RS).- 3.9 RS Shape Correction Factors.- 3.10 Modified FPP Configurations.- 3.11 Temperature Correction.- 3.12 Other Resistivity Measuring Systems.- 3.13 Depletion Layer Capacitance Profiling.- 3.14 Junction Depth Determination.- 3.15 Film Thickness Measurement.- 3.16 Surface Profilers.- 4. Equilibrium Concepts.- 4.1 Definitions.- 4.2 Phase Rule.- 4.3 Unary Systems.- 4.4 Binary Systems.- 4.5 Isomorphous Binary Systems.- 4.6 Eutectic Binary Systems.- 4.7 Binary Systems; Complete Solid Insolubility.- 4.8 The Eutectic.- 4.9 Binary Systems; Partial Solid Solubility.- 4.10 Contact Formation Temperatures.- 4.11 Limit of Solid Solubility.- 4.12 Distribution Coefficient.- 4.13 Decant Refining.- 4.14 Congruent Transformations.- 4.15 Peritectic Transformations.- 4.16 Contact Systems.- 5. Oxidation.- 5.1 Structure.- 5.2 Phase Changes.- 5.3 Other Processing Glasses.- 5.4 Thermal Oxidation; Diffusion.- 5.5 Oxidation Model.- 5.6 Oxidation Plots.- 5.7 Computer Calculations.- 5.8 Special Oxidations.- 5.9 Oxidation of Silicon Nitride.- 5.10. Thickness Determination.- 6. Diffusion: Predeposition.- 6.1 Diffusion in Monocrystals.- 6.2 Fick’s Laws of Diffusion.- 6.3 Predeposition Diffusion (Case I).- 6.4 Predep Junction Formation.- 6.5 Calculation of Sheet Resistance.- 6.6 Oxide Masking.- 6.7 Processing Parameters and xj.- 6.8 Furnaces.- 6.9 Predep Sources.- 6.10 On-Wafer Sources.- 6.11 Off-Wafer Sources.- 6.12 Gas Primary Sources.- 6.13 Liquid Primary Sources.- 6.14 Solid Primary Sources.- 6.15 Predep Evaluation.- 6.16 Thermomigration.- 7. Diffusion; Redistribution.- 7.1 Drive Diffusion (Case IV).- 7.2 Drive Junction Formation.- 7.3 Time Dependent Diffusivity.- 7.4 BJT Processing Equations.- 7.5 Sheet Resistance.- 7.6 Outdiffusion into Growing Epitaxial Layers (Case V), Autodoping.- 7.7 Outdiffusion into Growing Oxide Layer (Case VI).- 7.8 Redistribution During Oxide CVD.- 7.9 Junction Formation by Outdiffusion (Case VII).- 7.10 Anomalous Profiles.- 7.11 Arsenic Emitter.- 7.12 Phosphorus Emitter.- 7.13 Correction for ? versus N Curve.- 8. Ion Implantation.- 8.1 Basic Mechanism.- 8.2 Generic Ion Implanter.- 8.3 Electric and Magnetic Deflection.- 8.4 Implanter Sections.- 8.5 Scanning.- 8.6 Process Chamber.- 8.7 Beam Current Measurement; Faraday Cups.- 8.8 Implant Profiles.- 8.9 Dose Calculation.- 8.10 Sheet Resistance.- 8.11 Masking.- 8.12 Radiation Damage.- 8.13 Annealing.- 8.14 Applications.- 8.15 Implantation in Compound Semiconductors.- 9. Chemical Vapor Deposition; Epitaxy.- 9.1 Basic Chemical Processes.- 9.2 Deposited Film Structure.- 9.3 Silicon Epitaxial System.- 9.4 Chemicals for Silicon Epitaxy.- 9.5 Gas-Flow Dynamics.- 9.6 Doping Considerations.- 9.7 Spurious Doping.- 9.8 Substrate Preparation.- 9.9 Deposition Cycle.- 9.10 Nonplanar Epi.- 9.11 Low-Pressure Epitaxy (LPE).- 9.12 Epi Layer Evaluation.- 9.13 CVD of Polycrystal and Amorphous Films.- 9.14 Low-Pressure CVD (LPCVD).- 9.15 Plasma-Enhanced CVD (PECVD).- 9.16 Photopyrolysis.- 9.17 Photolysis.- 9.18 Compound Semiconductors; MOCVD.- 10. Etching.- 10.1 Types; Processes.- 10.2 Wet Etching.- 10.3 Oxide Etching.- 10.4 Isotropic Si Etch.- 10.5 Anisotropic Si Etches.- 10.6 Anisotropic Si Etch: Applications.- 10.7 Other Insulator Etches.- 10.8 Metal Etches.- 10.9 Lift-Off Technique.- 10.10 Wafer Cleaning.- 10.11 Wet versus Dry Etching.- 10.12 Dry Etching.- 10.13 Plasma Etching Reactors.- 10.14 Endpoint Detection.- 10.15 Reactive Plasma Etching.- 10.16 Anisotropic Etching.- 10.17 Nonreactive Ion Etching: Sputtering.- 10.18 Reactive Ion Etching (RIE).- 10.19 Radiation Damage.- 10.20 Compound Semiconductors.- 11. Lithography.- 11.1 Pattern Transfer Processes.- 11.2 Mask-Based Photolithography.- 11.3 Global Aligners.- 11.4 Direct Step-on-Wafer System (DSW).- 11.5 Direct Write-on-Wafer (DWW).- 11.6 Photomasks.- 11.7 Photoresists.- 11.8 PR Application.- 11.9 PR Processing.- 11.10 Multilayer Photoresists.- 11.11 X-Ray Lithography (XRL).- 11.12 Electron Beam Lithography (EBL).- 12. Physical Vapor Deposition; Sputtering.- 12.1 Physical Vapor Deposition (PVD).- 12.2 Evaporation.- 12.3 Transit.- 12.4 Film Formation.- 12.5 Molecular Beam Epitaxy (MBE).- 12.6 Sputter Deposition.- 12.7 Plasma Environment.- 12.8 Setup.- 12.9 Film Formation.- 12.10 Alloys, Compounds, Reactive Sputtering.- 12.11 Planar Magnetron Sputtering.- 12.12 Bias Sputtering.- 12.13 Ion Plating.- Appendix A. Four-Point-Probe Derivations; Optical Interference.- A.1 Semi-Infinite (S-I) Sample.- A.2 Thickness Correction for l-t Samples.- A.3 Logarithmic Potential Derivation for Thin Samples.- A.4 Optical Interference.- Appendix B. Ion/Field Interactions.- Appendix C. The Glow Discharge.- C.1 General Gas Discharge.- C.2 The Glow.- C.3 A-C/R-F Glow Discharge.- C.4 R-F Problems.- C.5 Modified Techniques.- Appendix D. Gas Systems.- D.1 Basic Concepts.- D.2 Conductance Calculations.- D.3 Gas Supply Systems.- D.4 Gas Distribution Systems.- D.5 Exhaust Pump Considerations.- F.5.4. Dry Oxidation Curves for (111) Silicon Showing the Effect of Oxidant Pressure.- F.5.5. Dry Oxidation Curves of (111) Silicon with Added Chlorides.- F.5.6. Wet Oxidation of (111) Silicon and Silicon Nitride.- F.5.7. MBASIC Program for Oxidation of Silicon at Atmospheric Pressure.- F.6.1. Diffusion Data.- F.6.2. Error Function Properties.- F.6.3. Error Function Table.- F.6.5. Irvin Sheet Resistance Curves.- F.6.6. Oxide Masking Curves for Boron Predep.- F.6.7. Oxide Masking Curves for Phosphorus Predep.- F.6.8. Vapor Pressure Curves of Liquid Predep Sources.- F.6.10 Boron Nitride Predep Curves.- F.8.1. Ion Implantation: Effective Range Data.- Appendix G. Numerical Constants.- Appendix H. Furnace Construction.
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Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Planar Processing Primer is based on lecture notes for a silicon planar process ing lecture/lab course offered at the University of Illinois-UC for over fifteen years. Directed primarily to electrical engineering upperclassmen and graduate students, the material also has been used successfully by graduate students in physics and ceramic and metallurgical engineering. It is suitable for self-study by engineers trained in other disciplines who are beginning work in the semiconductor fields, and it can make circuit design engineers aware of the processing limitations under which they must work. The text describes and explains, at an introductory level, the principal processing steps used to convert raw silicon into a semiconductor device or integrated circuit. First-order models are used for theoretical treatments (e.g., of diffusion and ion implantation), with reference made to more advanced treatments, to computer programs such as SUPREM that include higher order effects, and to interactions among sequential processes. In Chapters 8, 9, and to, the application of silicon processes to compound semiconductors is discussed briefly. Over the past several years, the size of transistors has decreased markedly, allowing more transistors per chip unit area, and chip size has increased. 652 pp. Englisch. Codice articolo 9789401066822
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Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Planar Processing Primer is based on lecture notes for a silicon planar process ing lecture/lab course offered at the University of Illinois-UC for over fifteen years. Directed primarily to electrical engineering upperclassmen and graduate students, the material also has been used successfully by graduate students in physics and ceramic and metallurgical engineering. It is suitable for self-study by engineers trained in other disciplines who are beginning work in the semiconductor fields, and it can make circuit design engineers aware of the processing limitations under which they must work. The text describes and explains, at an introductory level, the principal processing steps used to convert raw silicon into a semiconductor device or integrated circuit. First-order models are used for theoretical treatments (e.g., of diffusion and ion implantation), with reference made to more advanced treatments, to computer programs such as SUPREM that include higher order effects, and to interactions among sequential processes. In Chapters 8, 9, and to, the application of silicon processes to compound semiconductors is discussed briefly. Over the past several years, the size of transistors has decreased markedly, allowing more transistors per chip unit area, and chip size has increased.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 652 pp. Englisch. Codice articolo 9789401066822
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