Logic Synthesis and Soc Prototyping: Rtl Design Using Vhdl - Brossura

Taraate, Vaibbhav

 
9789811513169: Logic Synthesis and Soc Prototyping: Rtl Design Using Vhdl
Brossura
ISBN 10: 9811513163 ISBN 13: 9789811513169
Casa editrice: Springer Nature, 2021

Sinossi

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.


Le informazioni nella sezione "Riassunto" possono far riferimento a edizioni diverse di questo titolo.

Informazioni sull?autore

Vaibbhav Taraate is Entrepreneur and Mentor at “1 Rupee S T”. He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur, in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 15 years ofexperience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.

Dalla quarta di copertina

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.


Le informazioni nella sezione "Su questo libro" possono far riferimento a edizioni diverse di questo titolo.

Editore
Springer Nature
Data di pubblicazione
2021
Lingua
Inglese
ISBN 10 
9811513163
ISBN 13 
9789811513169
Rilegatura
Copertina flessibile
Numero edizione
1
Numero di pagine
272
Contatto del produttore
ProductSafety@springernature.com
ProductSafety@springernature.com

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Darmstadt
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Germania

Altre edizioni note dello stesso titolo

9789811513138: Logic Synthesis and SOC Prototyping: RTL Design Using VHDL

Edizione in evidenza

ISBN 10:  9811513139 ISBN 13:  9789811513138
Casa editrice: Springer Nature, 2020
Rilegato