Electromigration Modeling at Circuit Layout Level - Brossura

Tan, Cher Ming; He, Feifei

Brossura

ISBN 10: 9814451207 ISBN 13: 9789814451208

Casa editrice: Springer, 2013

Riassunto

Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels. Electromigration (EM) of interconnects has now become the dominant failure mechanism that determines the circuit reliability. This brief addresses the readers to the necessity of 3D real circuit modelling in order to evaluate the EM of interconnect system in ICs, and how they can create such models for their own applications. A 3-dimensional (3D) electro-thermo-structural model as opposed to the conventional current density based 2-dimensional (2D) models is presented at circuit-layout level.

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Informazioni sull'autore

Dr Tan is a member of the academic staff at the Nanyang Technological University, Singapore, and has been working on interconnect reliability for more than 10 years. He has published more than 150 technical papers in this area. His work includes the numerical modeling of interconnect reliability, reliability physics of interconnects, testing methodologies of interconnect reliability, failure analysis of interconnects, and statistical analysis of interconnect reliability data. He has trained several research staff in this area, including research fellows, research associates, PhD students and industrial engineers. He has had published a 173-page review article on electromigration in the Material Science and Engineering Review, and is the sole author of the book Electromigration in ULSI Interconnection, published by World Scientific. He is currently IEEE Distinguished Lecturer in the area of reliability, Fellow of Singapore Quality Institute, and Senior Member of ASQ and IEEE. Dr. Li received his B.Eng and PhD from the School of Electrical and Electronic Engineering at Nanyang Technological University (NTU), Singapore, in 2005 and 2009 respectively. He was Process Integration Engineer in Systems on Silicon Manufacturing Co Pte Ltd (SSMC) from 2007 to 2009. He is one of the five recipients of the global inaugural prestige 2007 IEEE Electronic Device Society Master's Student Fellowship. In 2009, he joined the Singapore Institute of Manufacturing Technology (SIMTech), one of the research institutes in the Agency of Science, Technology and Research (A*STAR), as research scientist. His research interests include IC interconnection reliability and modeling, semiconductor device physics and reliability. Dr Gan has extensive hands-on experience, beginning in 2001, in the application of the finite element method to reliability analysis. He has over 10 years of diverse technical and management experience in research and development of semiconductor reliability solutions and ideas on manufacturing. From 2001 to 2006, he was a research fellow with the School of Electrical and Electronic Engineering and School of Materials Science and Engineering, Nanyang Technological University, Singapore. In 2006, he joined Semiconductor Manufacturing International Corporation (SMIC), Shanghai, China, as a principal engineer in the Logic Technology Development Center. He is currently a reliability senior manager in the Technology R&D Center, managing a team responsible for process reliability improvement and evaluation (both FEOL and BEOL) for advanced technology nodes. Dr Gan has had more than 50 technical papers on finite element methods, ULSI interconnect reliability, and semiconductor reliability, published in refereed journals and international conferences, and 10 patents filed in China. Dr Hou received his B.Eng and PhD from the School of Electrical and Electronic Engineering at Nanyang Technological University (NTU), Singapore, in 2005 and 2010 respectively. He has been working as a process integration engineer in Systems on Silicon Manufacturing Co Pte Ltd (SSMC) since 2009. His research interests are electromigration and stress induced voiding in IC interconnections.

Dettagli dell'edizione

• Editore: Springer
• Data di pubblicazione: 2013
• Lingua: Inglese
• ISBN 10: 9814451207
• ISBN 13: 9789814451208
• Rilegatura: Copertina flessibile
• Numero di pagine: 103
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