Defect-oriented Testing for Nano-metric CMOS VLSI Circuits

Sachdev, Manoj; Gyvez, Jose Pineda de

ISBN 10: 0387465464 / ISBN 13: 9780387465463

Editore: Springer-Verlag New York Inc., 2007

Riguardo questo articolo

Presents the work on defect-oriented testing. This book is useful for test and design practitioners from academia and industry. Series: Frontiers in Electronic Testing. Num Pages: 349 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational. Dimension: 234 x 156 x 20. Weight in Grams: 669. . 2007. 2nd ed. 2007. Hardback. . . . .

Codice articolo V9780387465463

Dati bibliografici

• Titolo: Defect-oriented Testing for Nano-metric CMOS VLSI Circuits
• Editore: Springer-Verlag New York Inc.
• Data di pubblicazione: 2007
• Lingua: Inglese
• ISBN 10: 0387465464
• ISBN 13: 9780387465463
• Rilegatura: Rilegato
• Edizione: seconda edizione
• Condizione: New

Descrizione articolo

Riassunto

The 2^nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.

Dalla quarta di copertina

Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts.

The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.