Robust SRAM Designs and Analysis. Questo articolo non è disponibile.
Lingua: inglese
Editore: Springer New York, 2012
- Rilegato
- Usato
Da: Buchpark, Trebbin, GermaniaBuchpark
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EUR 82,42
Descrizione dell’articolo da parte del venditore
Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.Provides a complete and concise introduction to SRAM bitcell design and analysis; Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis;Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices;Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.…
Codice articolo 11836525/12
- Titolo
- Robust SRAM Designs and Analysis
- Autore
- Jawar Singh, Dhiraj K. Pradhan, Saraju P. Mohanty
- Editore
- Springer New York
- Anno di pubblicazione
- 2012
- Condizione
- Sehr gut
- Rilegatura
- Rilegato
- Lingua
- inglese
- ISBN 10
- 1461408172
- ISBN 13
- 9781461408178
- Cataloghi dei venditori
- Bücher
This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.
- Provides a complete and concise introduction to SRAM bitcell design and analysis;
- Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis;
- Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices;
- Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.
"Riassunto" può appartenere a un’altra edizione di questo titolo.
Dalla quarta di copertina
This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.
- Provides a complete and concise introduction to SRAM bitcell design and analysis;
- Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis;
- Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices;
- Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.
"Descrizione articolo" può appartenere a un’altra edizione di questo titolo.