Transactions on High-Performance Embedded Architectures and Compilers II. Questo articolo non è disponibile.Transactions on High-Performance Embedded Architectures and Compilers II

caches.Theyintroduce a reuse-distance drowsy cache mechanism that issimpleas well as e?ective in reducingthestaticpower in caches.

Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems.

This second issue contains 15 papers carefully reviewed and selected out of 31 submissions and is divided into two sections. The first section contains extended versions of the top five papers from the 2nd International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2007) held in Ghent, Belgium, in January 2007.  The second section consists of ten papers covering topics such as microarchitecture, memory systems, code generation, and performance modeling.