Wafer-Level Testing and Test During Burn-In for Integrated Circuits (Artech House Integrated Microsystems)

Bahukudumbi, Sudarshan; Chakrabarty, Krishnendu

ISBN 10: 1596939893 / ISBN 13: 9781596939899

Editore: Artech House Publishers, 2010

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Titolo: Wafer-Level Testing and Test During Burn-In ...

Casa editrice: Artech House Publishers

Data di pubblicazione: 2010

Legatura: Hardcover

Condizione: New

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Riassunto:

Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.

Product Description:

Book by Bahukudumbi Sudarshan Chakrabarty Krishnendu