Wafer-Level Testing and Test During Burn-In for Integrated Circuits

Sudarshan Bahukudumbi and Krishnendu Chakrabarty

ISBN 10: 1596939893 / ISBN 13: 9781596939899

Editore: Artech House, 2010

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Codice articolo MA 9781596939899

Dati bibliografici

• Titolo: Wafer-Level Testing and Test During Burn-In for Integrated Circuits
• Editore: Artech House
• Data di pubblicazione: 2010
• Lingua: Inglese
• ISBN 10: 1596939893
• ISBN 13: 9781596939899
• Rilegatura: Hardcover
• Condizione: New

Descrizione articolo

Riassunto

Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.

Product Description

Book by Bahukudumbi Sudarshan Chakrabarty Krishnendu