Retargetable Code Generation for Digital Signal Processors

Leupers, Rainer (Marwedel, Peter)

ISBN 10: 0792399587 / ISBN 13: 9780792399582

Editore: Kluwer Academic Publishers, Dordrecht, The Netherlands, 1997

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Hardcover with very slight signs of corner wear and contents in very good clean condition. Previous owner's name on FEP. No dust jacket. T.

Codice articolo 249147

Dati bibliografici

• Titolo: Retargetable Code Generation for Digital Signal Processors
• Editore: Kluwer Academic Publishers, Dordrecht, The Netherlands
• Data di pubblicazione: 1997
• Lingua: Inglese
• ISBN 10: 0792399587
• ISBN 13: 9780792399582
• Rilegatura: hardcover
• Edizione: First Edition.
• Condizione: Very Good
• Condizione della sovraccoperta: No Dust Jacket
• Tipo di libro: Used
• Cataloghi dei venditori:
  • Science - Electronics

Descrizione articolo

Riassunto

According to market analysts, the market for consumer electronics will con­ tinue to grow at a rate higher than that of electronic systems in general. The consumer market can be characterized by rapidly growing complexities of appli­ cations and a rather short market window. As a result, more and more complex designs have to be completed in shrinking time frames. A key concept for coping with such stringent requirements is re-use. Since the re-use of completely fixed large hardware blocks is limited to subproblems of system-level applications (for example MPEG-2), flexible, programmable pro­ cessors are being used as building blocks for more and more designs. Processors provide a unique combination offeatures: they provide flexibility and re-use. The processors used in consumer electronics are, however, in many cases dif­ ferent from those that are used for screen and keyboard-based equipment, such as PCs. For the consumer market in particular, efficiency of the product plays a dominating role. Hence, processor architectures for these applications are usually highly-optimized and tailored towards a certain application domain.

Contenuti

Foreword. Preface. 1. Introduction. 2. Processor Modelling. 3. Instruction-Set Extraction. 4. Code Generation. 5. Instruction-Level Parallelism. 6. The Record Compiler. 7. Conclusions. References. Index.