Hardcover. Condizione: Very Good. No Jacket. May have limited writing in cover pages. Pages are unmarked. ~ ThriftBooks: Read More, Spend Less.
Condizione: New. pp. 180.
Da: Ria Christie Collections, Uxbridge, Regno Unito
EUR 115,69
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Da: Ria Christie Collections, Uxbridge, Regno Unito
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Aggiungi al carrelloCondizione: New. pp. 180 40 Illus. (32 Col.).
EUR 113,07
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Aggiungi al carrelloPaperback. Condizione: New.
Da: Biblios, Frankfurt am main, HESSE, Germania
EUR 123,23
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Aggiungi al carrelloCondizione: New. pp. 180.
Condizione: New. pp. 169.
Da: Revaluation Books, Exeter, Regno Unito
EUR 154,57
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Aggiungi al carrelloHardcover. Condizione: Brand New. 2014 edition. 169 pages. 9.25x6.25x0.50 inches. In Stock.
EUR 95,15
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Aggiungi al carrelloTaschenbuch. Condizione: Neu. Pipelined Multiprocessor System-on-Chip for Multimedia | Haris Javaid (u. a.) | Taschenbuch | viii | Englisch | 2016 | Springer | EAN 9783319347110 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.
EUR 152,82
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Aggiungi al carrelloPaperback. Condizione: Brand New. reprint edition. 180 pages. 9.25x6.10x0.43 inches. In Stock.
EUR 90,48
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Aggiungi al carrelloCondizione: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors¿ combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.
Da: Mispah books, Redhill, SURRE, Regno Unito
EUR 185,08
Quantità: 1 disponibili
Aggiungi al carrelloPaperback. Condizione: Like New. Like New. book.
Da: Mispah books, Redhill, SURRE, Regno Unito
EUR 185,08
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Aggiungi al carrelloHardcover. Condizione: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
Da: Brook Bookstore On Demand, Napoli, NA, Italia
EUR 86,24
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Aggiungi al carrelloCondizione: new. Questo è un articolo print on demand.
Da: Brook Bookstore On Demand, Napoli, NA, Italia
EUR 86,24
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Aggiungi al carrelloCondizione: new. Questo è un articolo print on demand.
Lingua: Inglese
Editore: Springer International Publishing, 2016
ISBN 10: 331934711X ISBN 13: 9783319347110
Da: moluna, Greven, Germania
EUR 92,27
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Aggiungi al carrelloCondizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Describes the state-of-the-art on pipeline-level parallelism and multimedia MPSoCsIncludes analytical models and estimation methods for performance estimation of pipelined MPSoCsCovers several design space exploration techniques for pipelin.
Lingua: Inglese
Editore: Springer International Publishing, 2013
ISBN 10: 331901112X ISBN 13: 9783319011127
Da: moluna, Greven, Germania
EUR 92,27
Quantità: Più di 20 disponibili
Aggiungi al carrelloCondizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Describes the state-of-the-art on pipeline-level parallelism and multimedia MPSoCsIncludes analytical models and estimation methods for performance estimation of pipelined MPSoCsCovers several design space exploration techniques for pipelin.
Da: Majestic Books, Hounslow, Regno Unito
EUR 143,79
Quantità: 4 disponibili
Aggiungi al carrelloCondizione: New. Print on Demand pp. 169.
Da: Biblios, Frankfurt am main, HESSE, Germania
EUR 143,77
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Aggiungi al carrelloCondizione: New. PRINT ON DEMAND pp. 169.
Lingua: Inglese
Editore: Springer, Palgrave Macmillan Aug 2016, 2016
ISBN 10: 331934711X ISBN 13: 9783319347110
Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germania
EUR 106,99
Quantità: 1 disponibili
Aggiungi al carrelloTaschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors¿ combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 180 pp. Englisch.
Lingua: Inglese
Editore: Springer, Palgrave Macmillan Dez 2013, 2013
ISBN 10: 331901112X ISBN 13: 9783319011127
Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germania
EUR 106,99
Quantità: 1 disponibili
Aggiungi al carrelloBuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors¿ combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 180 pp. Englisch.