Jayaram natarajan (10 risultati)
- Brossura
Da: Majestic Books, Hounslow, Regno UnitoMajestic Books
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 11,27
EUR 7,60 spedizioneSpedito da Regno Unito a U.S.A.Quantità: 4 disponibili
Condizione: New. pp. 306.
- Brossura
Da: Books Puddle, New York, NY, U.S.A.Books Puddle
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 105,74
EUR 3,46 spedizioneSpedito in U.S.A.Quantità: 4 disponibili
Condizione: New.
- Brossura
Da: Mispah books, Redhill, SURRE, Regno UnitoMispah books
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 156,49
EUR 29,22 spedizioneSpedito da Regno Unito a U.S.A.Quantità: 1 disponibili
paperback. Condizione: New. NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
- Altre immagini
- Brossura
- Print on Demand
Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermaniaBuchWeltWeit Ludwig Meier e.K.
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 67,90
EUR 23,00 spedizioneSpedito da Germania a U.S.A.Quantità: 2 disponibili
Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -One of the challenges faced today in the design of microprocessors is to obtain energy efficiency, speed and reliability at the same time with technology scaling, in the face of extreme process variations. The variation in delay be…havior of the same design within-die and die-to-die increases significantly at technology nodes below 10nm. In addition, timing variations during chip operation occur due to dynamically changing factors like workload, temperature, aging. To guarantee lifetime operational correctness under timing uncertainties, safety margins in the form of one-time worst-case guard-bands are incorporated into the design resulting in energy-speed inefficiencies. This book does literature survey of the digital design and micro-architectural techniques in literature to tackle the above challenges. Two methods are described in detail (1) A low cost post-manufacturing self-testing and speed-tuning methodology to top-up speed coverage and find the maximum reliable clock frequency of each processor pipeline in a multi-processor system (2) Design and operation of a novel timing variation tolerant pipeline design, which eliminates the need to incorporate timing safety margins. 136 pp. Englisch.
- Altre immagini
- Brossura
- Print on Demand
Da: moluna, Greven, Germaniamoluna
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 55,14
EUR 48,99 spedizioneSpedito da Germania a U.S.A.Quantità: Più di 20 disponibili
Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Natarajan JayaramJayaram Natarajan was born in Mumbai, India and received his BS in Electronics Engineering from University of Mumbai, MS and PhD in Electrical and Computer Engineering from Georgia Ins…titute of Technology, Atlanta. H.
- Brossura
- Print on Demand
Da: Majestic Books, Hounslow, Regno UnitoMajestic Books
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 109,32
EUR 7,60 spedizioneSpedito da Regno Unito a U.S.A.Quantità: 4 disponibili
Condizione: New. Print on Demand.
- Brossura
- Print on Demand
Da: Biblios, frankfurt am main, HESSE, GermaniaBiblios
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 110,26
EUR 9,95 spedizioneSpedito da Germania a U.S.A.Quantità: 4 disponibili
Condizione: New. PRINT ON DEMAND.
- Altre immagini
- Brossura
- Print on Demand
Da: preigu, Osnabrück, Germaniapreigu
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 57,25
EUR 70,00 spedizioneSpedito da Germania a U.S.A.Quantità: 5 disponibili
Taschenbuch. Condizione: Neu. Energy Efficient and Fault-tolerant Computing | A comprehensive manual on hardware and micro-architecture techniques for fault-tolerance, low power and high performance | Jayaram Natarajan | Taschenbuch | 136 S. | Englisch | 2019 | Scholars' Press | EAN 9786138916208 | Verantwortliche Person für die… EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu Print on Demand.
- Altre immagini
- Brossura
- Print on Demand
Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germaniabuchversandmimpf2000
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 67,90
EUR 60,00 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -One of the challenges faced today in the design of microprocessors is to obtain energy efficiency, speed and reliability at the same time with technology scaling, in the face of extreme process variations. The variation in delay behavi…or of the same design within-die and die-to-die increases significantly at technology nodes below 10nm. In addition, timing variations during chip operation occur due to dynamically changing factors like workload, temperature, aging. To guarantee lifetime operational correctness under timing uncertainties, safety margins in the form of one-time worst-case guard-bands are incorporated into the design resulting in energy-speed inefficiencies. This book does literature survey of the digital design and micro-architectural techniques in literature to tackle the above challenges. Two methods are described in detail (1) A low cost post-manufacturing self-testing and speed-tuning methodology to top-up speed coverage and find the maximum reliable clock frequency of each processor pipeline in a multi-processor system (2) Design and operation of a novel timing variation tolerant pipeline design, which eliminates the need to incorporate timing safety margins.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 136 pp. Englisch.
- Altre immagini
- Brossura
- Print on Demand
Da: AHA-BUCH GmbH, Einbeck, GermaniaAHA-BUCH GmbH
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 68,71
EUR 61,11 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - One of the challenges faced today in the design of microprocessors is to obtain energy efficiency, speed and reliability at the same time with technology scaling, in the face of extreme process variations. The variation in delay behavio…r of the same design within-die and die-to-die increases significantly at technology nodes below 10nm. In addition, timing variations during chip operation occur due to dynamically changing factors like workload, temperature, aging. To guarantee lifetime operational correctness under timing uncertainties, safety margins in the form of one-time worst-case guard-bands are incorporated into the design resulting in energy-speed inefficiencies. This book does literature survey of the digital design and micro-architectural techniques in literature to tackle the above challenges. Two methods are described in detail (1) A low cost post-manufacturing self-testing and speed-tuning methodology to top-up speed coverage and find the maximum reliable clock frequency of each processor pipeline in a multi-processor system (2) Design and operation of a novel timing variation tolerant pipeline design, which eliminates the need to incorporate timing safety margins.
