Nandyala naveena (9 risultati)

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  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing, 2020

    620268514X / 9786202685146

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    Da: Books Puddle, Woodside, NY, U.S.A.Books Puddle

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    Condizione: Nuovo

    EUR 65,12

    EUR 3,50 spedizione 
    Spedito in U.S.A.

    Quantità: 4 disponibili

    Condizione: New.

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing, 2020

    620268514X / 9786202685146

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    Da: moluna, Greven, Germaniamoluna

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    Condizione: Nuovo

    EUR 34,25

    EUR 48,99 spedizione 
    Spedito da Germania a U.S.A.

    Quantità: Più di 20 disponibili

    Condizione: New.

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing, 2020

    620268514X / 9786202685146

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    Da: Mispah books, Redhill, SURRE, Regno UnitoMispah books

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    Condizione: Nuovo

    EUR 144,91

    EUR 29,07 spedizione 
    Spedito da Regno Unito a U.S.A.

    Quantità: 1 disponibili

    paperback. Condizione: New. NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing Jul 2020, 2020

    620268514X / 9786202685146

    • Brossura
    • Print on Demand

    Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermaniaBuchWeltWeit Ludwig Meier e.K.

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    Condizione: Nuovo

    EUR 39,90

    EUR 23,00 spedizione 
    Spedito da Germania a U.S.A.

    Quantità: 2 disponibili

    Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -With rapid development of portable digital applications, the demand for increasing speed, compact implementation and low power dissipation triggers numerous research efforts. GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is proposed. This technique allows minimization of power consumption and area. Performance comparison with traditional CMOS with respect to the layout area, number of devices and power dissipation, and showing advantages of GDI. The power consumption for CMOS schematic design are as follows AND gate (7.39nW), OR gate (5.118nW), XOR gate (620nW), 2:1 Multiplexer (2.705µW), Full Adder (42.285µW), D Flip-Flop (6.422µW). In this paper we have achieved low power using GDI for AND gate, OR gate, XOR gate, 2:1Multiplexer, Full Adder and D-FlipFlop 0.0001nW, 0.00002nW, 1.78nW, 0.01nW, 11.75µW, 3.325µW respectively for supply voltage 1.2V. The Area reduced for GDI AND gate is (66.6%), OR gate (66.6%), XOR gate (71.4%), 2:1 Multiplexer (83.33%), Full Adder( 78.26%) and D Flip Flop (33.33%) compared to CMOS technology. In this project the Microwind 2 used for Layout design and DSCH 2 used for schematic design with 120nm technology. 60 pp. Englisch. …

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing, 2020

    620268514X / 9786202685146

    • Brossura
    • Print on Demand

    Da: Majestic Books, Hounslow, Regno UnitoMajestic Books

    Venditore con 4 stelle
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    Condizione: Nuovo

    EUR 64,21

    EUR 7,56 spedizione 
    Spedito da Regno Unito a U.S.A.

    Quantità: 4 disponibili

    Condizione: New. Print on Demand.

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing, 2020

    620268514X / 9786202685146

    • Brossura
    • Print on Demand

    Da: Biblios, frankfurt am main, HESSE, GermaniaBiblios

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    Condizione: Nuovo

    EUR 64,95

    EUR 9,95 spedizione 
    Spedito da Germania a U.S.A.

    Quantità: 4 disponibili

    Condizione: New. PRINT ON DEMAND.

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing, 2020

    620268514X / 9786202685146

    • Brossura
    • Print on Demand

    Da: AHA-BUCH GmbH, Einbeck, GermaniaAHA-BUCH GmbH

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    Condizione: Nuovo

    EUR 43,00

    EUR 35,00 spedizione 
    Spedito da Germania a U.S.A.

    Quantità: 1 disponibili

    Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - With rapid development of portable digital applications, the demand for increasing speed, compact implementation and low power dissipation triggers numerous research efforts. GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is proposed. This technique allows minimization of power consumption and area. Performance comparison with traditional CMOS with respect to the layout area, number of devices and power dissipation, and showing advantages of GDI. The power consumption for CMOS schematic design are as follows AND gate (7.39nW), OR gate (5.118nW), XOR gate (620nW), 2:1 Multiplexer (2.705µW), Full Adder (42.285µW), D Flip-Flop (6.422µW). In this paper we have achieved low power using GDI for AND gate, OR gate, XOR gate, 2:1Multiplexer, Full Adder and D-FlipFlop 0.0001nW, 0.00002nW, 1.78nW, 0.01nW, 11.75µW, 3.325µW respectively for supply voltage 1.2V. The Area reduced for GDI AND gate is (66.6%), OR gate (66.6%), XOR gate (71.4%), 2:1 Multiplexer (83.33%), Full Adder( 78.26%) and D Flip Flop (33.33%) compared to CMOS technology. In this project the Microwind 2 used for Layout design and DSCH 2 used for schematic design with 120nm technology.…

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing Jul 2020, 2020

    620268514X / 9786202685146

    • Brossura
    • Print on Demand

    Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germaniabuchversandmimpf2000

    Venditore con 5 stelle
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    Condizione: Nuovo

    EUR 39,90

    EUR 60,00 spedizione 
    Spedito da Germania a U.S.A.

    Quantità: 1 disponibili

    Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -With rapid development of portable digital applications, the demand for increasing speed, compact implementation and low power dissipation triggers numerous research efforts. GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is proposed. This technique allows minimization of power consumption and area. Performance comparison with traditional CMOS with respect to the layout area, number of devices and power dissipation, and showing advantages of GDI. The power consumption for CMOS schematic design are as follows AND gate (7.39nW), OR gate (5.118nW), XOR gate (620nW), 2:1 Multiplexer (2.705µW), Full Adder (42.285µW), D Flip-Flop (6.422µW). In this paper we have achieved low power using GDI for AND gate, OR gate, XOR gate, 2:1Multiplexer, Full Adder and D-FlipFlop 0.0001nW, 0.00002nW, 1.78nW, 0.01nW, 11.75µW, 3.325µW respectively for supply voltage 1.2V. The Area reduced for GDI AND gate is (66.6%), OR gate (66.6%), XOR gate (71.4%), 2:1 Multiplexer (83.33%), Full Adder( 78.26%) and D Flip Flop (33.33%) compared to CMOS technology. In this project the Microwind 2 used for Layout design and DSCH 2 used for schematic design with 120nm technology.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 60 pp. Englisch.…

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing, 2020

    620268514X / 9786202685146

    • Brossura
    • Print on Demand

    Da: preigu, Osnabrück, Germaniapreigu

    Venditore con 5 stelle
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    Condizione: Nuovo

    EUR 35,60

    EUR 70,00 spedizione 
    Spedito da Germania a U.S.A.

    Quantità: 5 disponibili

    Taschenbuch. Condizione: Neu. GDI: Power & Area Efficient Digital Circuits for Portable Devices | Nandyala Naveena (u. a.) | Taschenbuch | Englisch | 2020 | LAP LAMBERT Academic Publishing | EAN 9786202685146 | Verantwortliche Person für die EU: LAP Lambert Academic Publishing, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu Print on Demand. …