Nandyala naveena (9 risultati)

GDI: Power & Area Efficient Digital Circuits for Portable Devices
Naveena, Nandyala; Poojitha, Nimmagadda; Rageshwari, Pallewar
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Da: Books Puddle, Woodside, NY, U.S.A.Books Puddle
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EUR 65,12
EUR 3,50 spedizioneSpedito in U.S.A.Quantità: 4 disponibili
Condizione: New.

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Da: moluna, Greven, Germaniamoluna
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 34,25
EUR 48,99 spedizioneSpedito da Germania a U.S.A.Quantità: Più di 20 disponibili
Condizione: New.

- Brossura
Da: Mispah books, Redhill, SURRE, Regno UnitoMispah books
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 144,91
EUR 29,07 spedizioneSpedito da Regno Unito a U.S.A.Quantità: 1 disponibili
paperback. Condizione: New. NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

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- Print on Demand
Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermaniaBuchWeltWeit Ludwig Meier e.K.
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 39,90
EUR 23,00 spedizioneSpedito da Germania a U.S.A.Quantità: 2 disponibili
Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -With rapid development of portable digital applications, the demand for increasing speed, compact implementation and low power dissipation triggers numerous research efforts. GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is proposed. This technique allows minimization of power consumption and area. Performance comparison with traditional CMOS with respect to the layout area, number of devices and power dissipation, and showing advantages of GDI. The power consumption for CMOS schematic design are as follows AND gate (7.39nW), OR gate (5.118nW), XOR gate (620nW), 2:1 Multiplexer (2.705µW), Full Adder (42.285µW), D Flip-Flop (6.422µW). In this paper we have achieved low power using GDI for AND gate, OR gate, XOR gate, 2:1Multiplexer, Full Adder and D-FlipFlop 0.0001nW, 0.00002nW, 1.78nW, 0.01nW, 11.75µW, 3.325µW respectively for supply voltage 1.2V. The Area reduced for GDI AND gate is (66.6%), OR gate (66.6%), XOR gate (71.4%), 2:1 Multiplexer (83.33%), Full Adder( 78.26%) and D Flip Flop (33.33%) compared to CMOS technology. In this project the Microwind 2 used for Layout design and DSCH 2 used for schematic design with 120nm technology. 60 pp. Englisch. …

GDI: Power & Area Efficient Digital Circuits for Portable Devices
Naveena, Nandyala; Poojitha, Nimmagadda; Rageshwari, Pallewar
- Brossura
- Print on Demand
Da: Majestic Books, Hounslow, Regno UnitoMajestic Books
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 64,21
EUR 7,56 spedizioneSpedito da Regno Unito a U.S.A.Quantità: 4 disponibili
Condizione: New. Print on Demand.

GDI: Power & Area Efficient Digital Circuits for Portable Devices
Naveena, Nandyala; Poojitha, Nimmagadda; Rageshwari, Pallewar
- Brossura
- Print on Demand
Da: Biblios, frankfurt am main, HESSE, GermaniaBiblios
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 64,95
EUR 9,95 spedizioneSpedito da Germania a U.S.A.Quantità: 4 disponibili
Condizione: New. PRINT ON DEMAND.

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- Print on Demand
Da: AHA-BUCH GmbH, Einbeck, GermaniaAHA-BUCH GmbH
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 43,00
EUR 35,00 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - With rapid development of portable digital applications, the demand for increasing speed, compact implementation and low power dissipation triggers numerous research efforts. GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is proposed. This technique allows minimization of power consumption and area. Performance comparison with traditional CMOS with respect to the layout area, number of devices and power dissipation, and showing advantages of GDI. The power consumption for CMOS schematic design are as follows AND gate (7.39nW), OR gate (5.118nW), XOR gate (620nW), 2:1 Multiplexer (2.705µW), Full Adder (42.285µW), D Flip-Flop (6.422µW). In this paper we have achieved low power using GDI for AND gate, OR gate, XOR gate, 2:1Multiplexer, Full Adder and D-FlipFlop 0.0001nW, 0.00002nW, 1.78nW, 0.01nW, 11.75µW, 3.325µW respectively for supply voltage 1.2V. The Area reduced for GDI AND gate is (66.6%), OR gate (66.6%), XOR gate (71.4%), 2:1 Multiplexer (83.33%), Full Adder( 78.26%) and D Flip Flop (33.33%) compared to CMOS technology. In this project the Microwind 2 used for Layout design and DSCH 2 used for schematic design with 120nm technology.…

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- Print on Demand
Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germaniabuchversandmimpf2000
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 39,90
EUR 60,00 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -With rapid development of portable digital applications, the demand for increasing speed, compact implementation and low power dissipation triggers numerous research efforts. GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is proposed. This technique allows minimization of power consumption and area. Performance comparison with traditional CMOS with respect to the layout area, number of devices and power dissipation, and showing advantages of GDI. The power consumption for CMOS schematic design are as follows AND gate (7.39nW), OR gate (5.118nW), XOR gate (620nW), 2:1 Multiplexer (2.705µW), Full Adder (42.285µW), D Flip-Flop (6.422µW). In this paper we have achieved low power using GDI for AND gate, OR gate, XOR gate, 2:1Multiplexer, Full Adder and D-FlipFlop 0.0001nW, 0.00002nW, 1.78nW, 0.01nW, 11.75µW, 3.325µW respectively for supply voltage 1.2V. The Area reduced for GDI AND gate is (66.6%), OR gate (66.6%), XOR gate (71.4%), 2:1 Multiplexer (83.33%), Full Adder( 78.26%) and D Flip Flop (33.33%) compared to CMOS technology. In this project the Microwind 2 used for Layout design and DSCH 2 used for schematic design with 120nm technology.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 60 pp. Englisch.…

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Da: preigu, Osnabrück, Germaniapreigu
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 35,60
EUR 70,00 spedizioneSpedito da Germania a U.S.A.Quantità: 5 disponibili
Taschenbuch. Condizione: Neu. GDI: Power & Area Efficient Digital Circuits for Portable Devices | Nandyala Naveena (u. a.) | Taschenbuch | Englisch | 2020 | LAP LAMBERT Academic Publishing | EAN 9786202685146 | Verantwortliche Person für die EU: LAP Lambert Academic Publishing, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu Print on Demand. …