Shivani madhok (59 risultati)

Condizione: New.

Taschenbuch. Condizione: Neu. Energy Efficient Design Techniques On FPGA | Low power Design Goal with Capacitance Scaling, Thermal Aware, HSTL, SSTL & LVCMOS IO Standard and Frequency Scaling | Shivani Madhok (u. a.) | Taschenbuch | 148 S. | Englisch | 2015 | LAP LAMBERT Academic Publishing | EAN 9783659357701 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.…

Condizione: New.

Condizione: New.

Condizione: New.

Condizione: New.

Condizione: New.

Taschenbuch. Condizione: Neu. Técnicas de design energeticamente eficientes em FPGA | Objetivo de design de baixo consumo de energia com dimensionamento de capacitância, sensibilidade térmica, HSTL, SSTL e LVCMOS IO Standard e dimensionamento de frequência | Shivani Madhok (u. a.) | Taschenbuch | Portugiesisch | 2025 | Edições Nosso Conhecimento | EAN 9786200684523 | Verantwortliche Person für die EU: SIA OmniScriptum Publishing, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu.…

Taschenbuch. Condizione: Neu. Techniki projektowania energooszcz¿dnego w uk¿adach FPGA | Cele projektowania energooszcz¿dnego z uwzgl¿dnieniem skalowania pojemno¿ci, wra¿liwo¿ci termicznej, standardów HSTL, SSTL i LVCMOS IO oraz skalowania cz¿stotliwo¿ci | Shivani Madhok (u. a.) | Taschenbuch | Polnisch | 2025 | Wydawnictwo Nasza Wiedza | EAN 9786200684363 | Verantwortliche Person für die EU: SIA OmniScriptum Publishing, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu.…

Condizione: New.

Condizione: New.

Condizione: New.

Condizione: New.

Taschenbuch. Condizione: Neu. Energieeffiziente Designtechniken für FPGAs | Ziel eines energiesparenden Designs mit Kapazitätsskalierung, thermischer Optimierung, HSTL, SSTL und LVCMOS-IO-Standard sowie Frequenzskalierung | Shivani Madhok (u. a.) | Taschenbuch | 136 S. | Deutsch | 2025 | Verlag Unser Wissen | EAN 9786200684370 | Verantwortliche Person für die EU: SIA OmniScriptum Publishing, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu.…

Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In this book we have designed 64 bit decoder, Internet of things (IoT)enable decoder, Energy Efficient Traffic Light Controller, Sensor based automatic barricades on public railway crossing, mobile charge sensor using LVCMOS IO Standard, Bio- Medical Wrist Watch, Unicode Reader of Greek, Latin and Sindhi, Digital Clock and FIR Filter using Verilog. And, we are using Design Goal, Capacitance Scaling, Frequency Scaling, Thermal Aware Design Approach, Clock Gating, Voltage Scaling, LVCMOS IO Standards, HSTL IO Standards, and SSTL IO Standards. We are using 28nm, 40nm Technology based latest Virtex-6, Kintex-7 and Artix-7 FPGA.We are using XPower Analyzer for Power Estimation and Xilinx for simulation of Hardware Description Language. In summary, we have covered more than 10 different Circuits and 10 different energy efficient technique that will help researcher, learner to learn these technique and apply these technique in their own design in order to make energy efficient design with Verilog. 148 pp. Englisch.…

Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - In this book we have designed 64 bit decoder, Internet of things (IoT)enable decoder, Energy Efficient Traffic Light Controller, Sensor based automatic barricades on public railway crossing, mobile charge sensor using LVCMOS IO Standard, Bio- Medical Wrist Watch, Unicode Reader of Greek, Latin and Sindhi, Digital Clock and FIR Filter using Verilog. And, we are using Design Goal, Capacitance Scaling, Frequency Scaling, Thermal Aware Design Approach, Clock Gating, Voltage Scaling, LVCMOS IO Standards, HSTL IO Standards, and SSTL IO Standards. We are using 28nm, 40nm Technology based latest Virtex-6, Kintex-7 and Artix-7 FPGA.We are using XPower Analyzer for Power Estimation and Xilinx for simulation of Hardware Description Language. In summary, we have covered more than 10 different Circuits and 10 different energy efficient technique that will help researcher, learner to learn these technique and apply these technique in their own design in order to make energy efficient design with Verilog.…

PAP. Condizione: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Madhok ShivaniShivani Madhok is an associate director of Gyancity Research lab. She has worked with researcher of more than 11 countries and have published 22 research papers in Springer, IEEE sponsored international conference. She .…

PAP. Condizione: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware 136 pp. Spanisch.

Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - En este libro hemos diseñado un decodificador de 64 bits, un decodificador habilitado para el Internet de las cosas (IoT), un controlador de semáforos energéticamente eficiente, barreras automáticas basadas en sensores para pasos a nivel públicos, un sensor de carga móvil que utiliza el estándar LVCMOS IO, un reloj de pulsera biomédico, un lector Unicode de griego, latín y sindhi, un reloj digital y un filtro FIR utilizando Verilog. Además, utilizamos objetivos de diseño, escalado de capacitancia, escalado de frecuencia, enfoque de diseño con reconocimiento térmico, sincronización de reloj, escalado de voltaje, estándares LVCMOS IO, estándares HSTL IO y estándares SSTL IO. Utilizamos la última tecnología Virtex-6, Kintex-7 y Artix-7 FPGA basada en 28 nm y 40 nm. Estamos utilizando XPower Analyzer para la estimación de potencia y Xilinx para la simulación del lenguaje de descripción de hardware. En resumen, hemos cubierto más de 10 circuitos diferentes y 10 técnicas de eficiencia energética diferentes que ayudarán a los investigadores y estudiantes a aprender estas técnicas y aplicarlas en sus propios diseños con el fin de crear diseños energéticamente eficientes con Verilog.…

Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware 136 pp. Französisch.

Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -In this book we have designed 64 bit decoder, Internet of things (IoT)enable decoder, Energy Efficient Traffic Light Controller, Sensor based automatic barricades on public railway crossing, mobile charge sensor using LVCMOS IO Standard, Bio- Medical Wrist Watch, Unicode Reader of Greek, Latin and Sindhi, Digital Clock and FIR Filter using Verilog. And, we are using Design Goal, Capacitance Scaling, Frequency Scaling, Thermal Aware Design Approach, Clock Gating, Voltage Scaling, LVCMOS IO Standards, HSTL IO Standards, and SSTL IO Standards. We are using 28nm, 40nm Technology based latest Virtex-6, Kintex-7 and Artix-7 FPGA.We are using XPower Analyzer for Power Estimation and Xilinx for simulation of Hardware Description Language. In summary, we have covered more than 10 different Circuits and 10 different energy efficient technique that will help researcher, learner to learn these technique and apply these technique in their own design in order to make energy efficient design with Verilog.OmniScriptum SRL, Str. Armeneasca 28/1, office 1, 2012 Chisinau 148 pp. Englisch.…

Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -En este libro hemos diseñado un decodificador de 64 bits, un decodificador habilitado para el Internet de las cosas (IoT), un controlador de semáforos energéticamente eficiente, barreras automáticas basadas en sensores para pasos a nivel públicos, un sensor de carga móvil que utiliza el estándar LVCMOS IO, un reloj de pulsera biomédico, un lector Unicode de griego, latín y sindhi, un reloj digital y un filtro FIR utilizando Verilog. Además, utilizamos objetivos de diseño, escalado de capacitancia, escalado de frecuencia, enfoque de diseño con reconocimiento térmico, sincronización de reloj, escalado de voltaje, estándares LVCMOS IO, estándares HSTL IO y estándares SSTL IO. Utilizamos la última tecnología Virtex-6, Kintex-7 y Artix-7 FPGA basada en 28 nm y 40 nm. Estamos utilizando XPower Analyzer para la estimación de potencia y Xilinx para la simulación del lenguaje de descripción de hardware. En resumen, hemos cubierto más de 10 circuitos diferentes y 10 técnicas de eficiencia energética diferentes que ayudarán a los investigadores y estudiantes a aprender estas técnicas y aplicarlas en sus propios diseños con el fin de crear diseños energéticamente eficientes con Verilog.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 136 pp. Spanisch.…

PAP. Condizione: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

PAP. Condizione: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

PAP. Condizione: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

PAP. Condizione: New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

PAP. Condizione: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.

PAP. Condizione: New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000.