Veidenbaum alex (8 risultati)
High Performance Computing: 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings (Lecture Notes in Computer Science)
Veidenbaum, Alex [Editor]; Joe, Kazuki [Editor]; Amano, Hideharu [Editor]; Aiso, Hideo [Editor];
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Paperback. Condizione: Very Good. Ex-library paperback in very nice condition with the usual markings and attachments. Text block clean and unmarked. Tight binding.
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Taschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - The 5th International Symposium on High Performance Computing (ISHPC-V) was held in Odaiba, Tokyo, Japan, October 20-22, 2003. The symposium was thoughtfully planned, organized, and supported by the ISHPC Organizing C- mittee and its collaborating… organizations. The ISHPC-V program included two keynote speeches, several invited talks, two panel discussions, and technical sessions covering theoretical and applied research topics in high-performance computing and representing both academia and industry. One of the regular sessions highlighted the research results of the ITBL project (IT-based research laboratory, ITBL is a Japanese national project started in 2001 with the objective of re- izing a virtual joint research environment using information technology. ITBL aims to connect 100 supercomputers located in main Japanese scienti c research laboratories via high-speed networks. A total of 58 technical contributions from 11 countries were submitted to ISHPC-V. Each paper received at least three peer reviews. After a thorough evaluation process, the program committee selected 14 regular (12-page) papers for presentation at the symposium. In addition, several other papers with fav- able reviews were recommended for a poster session presentation. They are also included in the proceedings as short (8-page) papers. Theprogramcommitteegaveadistinguishedpaperawardandabeststudent paper award to two of the regular papers. The distinguished paper award was given for 'Code and Data Transformations for Improving Shared Cache P- formance on SMT Processors' by Dimitrios S. Nikolopoulos. The best student paper award was given for 'Improving Memory Latency Aware Fetch Policies for SMT Processors' by Francisco J. Cazorla.
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Paperback. Condizione: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
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Hardcover. Condizione: Very Good. About like new with no marks. Sharp corners.
Innovative Architecture for Future Generation High-Performance Processors and Systems
International Workshop on Innovative Architecture, Maui High
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hardcover. Condizione: Very Good. Very Good. Dust Jacket may NOT BE INCLUDED.CDs may be missing. SHIPS FROM MULTIPLE LOCATIONS. book.
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Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermaniaBuchWeltWeit Ludwig Meier e.K.
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Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The 5th International Symposium on High Performance Computing (ISHPC-V) was held in Odaiba, Tokyo, Japan, October 20-22, 2003. The symposium was thoughtfully planned, organized, and supported by the ISHPC Organizing C- mittee and i…ts collaborating organizations. The ISHPC-V program included two keynote speeches, several invited talks, two panel discussions, and technical sessions covering theoretical and applied research topics in high-performance computing and representing both academia and industry. One of the regular sessions highlighted the research results of the ITBL project (IT-based research laboratory, ITBL is a Japanese national project started in 2001 with the objective of re- izing a virtual joint research environment using information technology. ITBL aims to connect 100 supercomputers located in main Japanese scienti c research laboratories via high-speed networks. A total of 58 technical contributions from 11 countries were submitted to ISHPC-V. Each paper received at least three peer reviews. After a thorough evaluation process, the program committee selected 14 regular (12-page) papers for presentation at the symposium. In addition, several other papers with fav- able reviews were recommended for a poster session presentation. They are also included in the proceedings as short (8-page) papers. Theprogramcommitteegaveadistinguishedpaperawardandabeststudent paper award to two of the regular papers. The distinguished paper award was given for 'Code and Data Transformations for Improving Shared Cache P- formance on SMT Processors' by Dimitrios S. Nikolopoulos. The best student paper award was given for 'Improving Memory Latency Aware Fetch Policies for SMT Processors' by Francisco J. Cazorla. 588 pp. Englisch.
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Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germaniabuchversandmimpf2000
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Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -The 5th International Symposium on High Performance Computing (ISHPC¿V) was held in Odaiba, Tokyo, Japan, October 20¿22, 2003. The symposium was thoughtfully planned, organized, and supported by the ISHPC Organizing C- mittee and its c…ollaborating organizations. The ISHPC-V program included two keynote speeches, several invited talks, two panel discussions, and technical sessions covering theoretical and applied research topics in high¿performance computing and representing both academia and industry. One of the regular sessions highlighted the research results of the ITBL project (IT¿based research laboratory, itbl.riken.go.jp/). ITBL is a Japanese national project started in 2001 with the objective of re- izing a virtual joint research environment using information technology. ITBL aims to connect 100 supercomputers located in main Japanese scienti c research laboratories via high¿speed networks. A total of 58 technical contributions from 11 countries were submitted to ISHPC-V. Each paper received at least three peer reviews. After a thorough evaluation process, the program committee selected 14 regular (12-page) papers for presentation at the symposium. In addition, several other papers with fav- able reviews were recommended for a poster session presentation. They are also included in the proceedings as short (8-page) papers. Theprogramcommitteegaveadistinguishedpaperawardandabeststudent paper award to two of the regular papers. The distinguished paper award was given for ¿Code and Data Transformations for Improving Shared Cache P- formance on SMT Processors¿ by Dimitrios S. Nikolopoulos. The best student paper award was given for ¿Improving Memory Latency Aware Fetch Policies for SMT Processors¿ by Francisco J. Cazorla.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 588 pp. Englisch.
