xue jingling (42 risultati)

Paperback. Condizione: Very Good. Ex-library paperback in very nice condition with the usual markings and attachments. Text block clean and unmarked. Tight binding.

Condizione: Good. Former library copy. Pages intact with minimal writing/highlighting. The binding may be loose and creased. Dust jackets/supplements are not included. Includes library markings. Stock photo provided. Product includes identifying sticker. Better World Books: Buy Books. Do Good.

Paperback. Condizione: Very Good. Ex-library paperback in very nice condition with the usual markings and attachments. Except for library markings, interior clean and unmarked. Tight binding.

2004. 16 x 24 cm. XVIII, 602 S. XVIII, 602 p. Softcover. Versand aus Deutschland / We dispatch from Germany via Air Mail. Einband bestoßen, daher Mängelexemplar gestempelt, sonst sehr guter Zustand. Imperfect copy due to slightly bumped cover, apart from this in very good condition. Stamped. (Lecture Notes in Computer Science). Sprache: Englisch.

Condizione: Brand New. New. US edition. Expediting shipping for all USA and Europe orders excluding PO Box. Excellent Customer Service.

Condizione: New. This is a Brand-new US Edition. This Item may be shipped from US or any other country as we have multiple locations worldwide.

Good. UK stocked, available immediately. Hardcover, published by Kluwer Academic Publishers in 2000. A withdrawn library copy with stamps and markings. The text is unmarked throughout, a good usable copy. Illustrated. Weight (unpacked) is 580 grams.

Condizione: New. In.

Condizione: New. In.

Condizione: New.

Condizione: New.

Condizione: New.

Hardcover. Condizione: New. In shrink wrap. Looks like an interesting title!

Taschenbuch. Condizione: Neu. Advances in Computer Systems Architecture | 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings | Thambipillai Srikanthan (u. a.) | Taschenbuch | xviii | Englisch | 2005 | Springer | EAN 9783540296430 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.

Taschenbuch. Condizione: Neu. Advances in Computer Systems Architecture | 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings | Pen-Chung Yew (u. a.) | Taschenbuch | Einband - flex.(Paperback) | Englisch | 2004 | Springer | EAN 9783540230038 | Verantwortliche Person für die EU: Springer-Verlag KG, Sachsenplatz 4-6, 1201 WIEN, ÖSTERREICH, productsafety[at]springernature[dot]com | Anbieter: preigu.

Condizione: New. In.

Condizione: New. In.

Taschenbuch. Condizione: Neu. Neuware -On behalf of the ProgramCommittee, we are pleased to present the proceedings of the 2005 Asia-Paci c Computer Systems Architecture Conference (ACSAC 2005) held in the beautiful and dynamic country of Singapore. This conference was the tenth in its series, one of the leading forums for sharing the emerging research ndings in this eld. In consultation with the ACSAC Steering Committee, we selected a - member Program Committee. This Program Committee represented a broad spectrum of research expertise to ensure a good balance of research areas, - stitutions and experience while maintaining the high quality of this conference series. This year¿s committee was of the same size as last year but had 19 new faces. We received a total of 173 submissions which is 14% more than last year. Each paper was assigned to at least three and in some cases four ProgramC- mittee members for review. Wherever necessary, the committee members called upon the expertise of their colleagues to ensure the highest possible quality in the reviewing process. As a result, we received 415 reviews from the Program Committee members and their 105 co-reviewers whose names are acknowledged inthe proceedings.Theconferencecommitteeadopteda systematicblind review process to provide a fair assessment of all submissions. In the end, we accepted 65 papers on a broad range of topics giving an acceptance rate of 37.5%. We are grateful to all the Program Committee members and the co-reviewers for their e orts in completing the reviews within a tight schedule.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 856 pp. Englisch.

Taschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - On behalf of the program committee, we were pleased to present this year's program for ACSAC: Asia-Paci c Computer Systems Architecture Conference. Now in its ninth year, ACSAC continues to provide an excellent forum for researchers, educators and practitioners to come to the Asia-Paci c region to exchange ideas on the latest developments in computer systems architecture. This year, the paper submission and review processes were semiautomated using the free version of CyberChair. We received 152 submissions, the largest number ever.Eachpaperwasassignedatleastthree,mostlyfour,andinafewcaseseven ve committee members for review. All of the papers were reviewed in a t- monthperiod,duringwhichtheprogramchairsregularlymonitoredtheprogress of the review process. When reviewers claimed inadequate expertise, additional reviewers were solicited. In the end, we received a total of 594 reviews (3.9 per paper) from committee members as well as 248 coreviewers whose names are acknowledged in the proceedings. We would like to thank all of them for their time and e ort in providing us with such timely and high-quality reviews, some of them on extremely short notice.

Taschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - On behalf of the ProgramCommittee, we are pleased to present the proceedings of the 2005 Asia-Paci c Computer Systems Architecture Conference (ACSAC 2005) held in the beautiful and dynamic country of Singapore. This conference was the tenth in its series, one of the leading forums for sharing the emerging research ndings in this eld. In consultation with the ACSAC Steering Committee, we selected a - member Program Committee. This Program Committee represented a broad spectrum of research expertise to ensure a good balance of research areas, - stitutions and experience while maintaining the high quality of this conference series. This year's committee was of the same size as last year but had 19 new faces. We received a total of 173 submissions which is 14% more than last year. Each paper was assigned to at least three and in some cases four ProgramC- mittee members for review. Wherever necessary, the committee members called upon the expertise of their colleagues to ensure the highest possible quality in the reviewing process. As a result, we received 415 reviews from the Program Committee members and their 105 co-reviewers whose names are acknowledged inthe proceedings.Theconferencecommitteeadopteda systematicblind review process to provide a fair assessment of all submissions. In the end, we accepted 65 papers on a broad range of topics giving an acceptance rate of 37.5%. We are grateful to all the Program Committee members and the co-reviewers for their e orts in completing the reviews within a tight schedule.

Paperback. Condizione: Brand New. 1st edition. 833 pages. 9.25x6.00x1.25 inches. In Stock.

Condizione: New.

Paperback. Condizione: Like New. Like New. book.

Taschenbuch. Condizione: Neu. Loop Tiling for Parallelism | Jingling Xue | Taschenbuch | xix | Englisch | 2012 | Springer | EAN 9781461369486 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.

Buch. Condizione: Neu. Neuware -Loop tiling, as one of the most important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for distributed memory machines. The author provides mathematical foundations, investigates loop permutability in the framework of nonsingular loop transformations, discusses the necessary machineries required, and presents state-of-the-art results for finding communication- and time-minimal tiling choices. Throughout the book, theorems and algorithms are illustrated with numerous examples and diagrams. The techniques presented in Loop Tiling for Parallelism can be adapted to work for a cluster of workstations, and are also directly applicable to shared-memory machines once the machines are modeled as BSP (Bulk Synchronous Parallel) machines.Features and key topics: Detailed review of the mathematical foundations, including convex polyhedra and cones;Self-contained treatment of nonsingular loop transformations, code generation, and full loop permutability;Tiling loop nests by rectangles and parallelepipeds, including their mathematical definition, dependence analysis, legality test, and code generation;A complete suite of techniques for generating SPMD code for a tiled loop nest;Up-to-date results on tile size and shape selection for reducing communication and improving parallelism;End-of-chapter references for further reading.Researchers and practitioners involved in optimizing compilers and students in advanced computer architecture studies will find this a lucid and well-presented reference work with numerous citations to original sources.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 280 pp. Englisch.

Taschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - Loop tiling, as one of the most important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for distributed memory machines. The author provides mathematical foundations, investigates loop permutability in the framework of nonsingular loop transformations, discusses the necessary machineries required, and presents state-of-the-art results for finding communication- and time-minimal tiling choices. Throughout the book, theorems and algorithms are illustrated with numerous examples and diagrams. The techniques presented in Loop Tiling for Parallelism can be adapted to work for a cluster of workstations, and are also directly applicable to shared-memory machines once the machines are modeled as BSP (Bulk Synchronous Parallel) machines. Features and key topics: Detailed review of the mathematical foundations, including convex polyhedra and cones; Self-contained treatment of nonsingular loop transformations, code generation, and full loop permutability; Tiling loop nests by rectangles and parallelepipeds, including their mathematical definition, dependence analysis, legality test, and code generation; A complete suite of techniques for generating SPMD code for a tiled loop nest; Up-to-date results on tile size and shape selection for reducing communication and improving parallelism; End-of-chapter references for further reading. Researchers and practitioners involved in optimizing compilers and students in advanced computer architecture studies will find this a lucid and well-presented reference work with numerous citations to original sources.

Buch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - Loop tiling, as one of the most important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for distributed memory machines. The author provides mathematical foundations, investigates loop permutability in the framework of nonsingular loop transformations, discusses the necessary machineries required, and presents state-of-the-art results for finding communication- and time-minimal tiling choices. Throughout the book, theorems and algorithms are illustrated with numerous examples and diagrams. The techniques presented in Loop Tiling for Parallelism can be adapted to work for a cluster of workstations, and are also directly applicable to shared-memory machines once the machines are modeled as BSP (Bulk Synchronous Parallel) machines. Features and key topics: Detailed review of the mathematical foundations, including convex polyhedra and cones; Self-contained treatment of nonsingular loop transformations, code generation, and full loop permutability; Tiling loop nests by rectangles and parallelepipeds, including their mathematical definition, dependence analysis, legality test, and code generation; A complete suite of techniques for generating SPMD code for a tiled loop nest; Up-to-date results on tile size and shape selection for reducing communication and improving parallelism; End-of-chapter references for further reading. Researchers and practitioners involved in optimizing compilers and students in advanced computer architecture studies will find this a lucid and well-presented reference work with numerous citations to original sources.

Condizione: As New. Unread book in perfect condition.

Hardcover. Condizione: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

Paperback. Condizione: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.