9783319604015 - gain-cell embedded drams for low-power vlsi systems-on-chip di meinerzhagen, pascal; teman, adam; giterman, robert; edri, noa; burg, andreas (12 risultati)
Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
Meinerzhagen, Pascal; Teman, Adam; Giterman, Robert; Edri, Noa; Burg, Andreas; Fish, Alexander
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Da: Ria Christie Collections, Uxbridge, Regno UnitoRia Christie Collections
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EUR 116,61
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Condizione: New. In.
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Da: AHA-BUCH GmbH, Einbeck, GermaniaAHA-BUCH GmbH
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EUR 106,99
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Buch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware h…igh-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
Meinerzhagen, Pascal; Teman, Adam; Giterman, Robert; Edri, Noa; Burg, Andreas; Fish, Alexander
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Da: Books Puddle, New York, NY, U.S.A.Books Puddle
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EUR 139,91
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Condizione: New.
Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
Pascal Meinerzhagen, Adam Teman, Robert Giterman, Noa Edri, Andreas Burg, Alexander Fish
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Da: Rarewaves.com USA, London, LONDO, Regno UnitoRarewaves.com USA
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EUR 145,14
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Hardback. Condizione: New. 1st ed. 2018. This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After… a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
Gain- Cell Embedded Drams for Low-power Vlsi Systems-on-chip
Meinerzhagen, Pascal/ Teman, Adam/ Giterman, Robert/ Edri, Noa/ Burg, Andreas
- Rilegato
Da: Revaluation Books, Exeter, Regno UnitoRevaluation Books
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EUR 152,02
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Hardcover. Condizione: Brand New. 146 pages. 9.25x6.25x0.50 inches. In Stock.
Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
Pascal Meinerzhagen, Adam Teman, Robert Giterman, Noa Edri, Andreas Burg, Alexander Fish
- Rilegato
Da: Rarewaves.com UK, London, Regno UnitoRarewaves.com UK
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EUR 141,73
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Hardback. Condizione: New. 1st ed. 2018. This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After… a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
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- Print on Demand
Da: Brook Bookstore On Demand, Napoli, NA, ItaliaBrook Bookstore On Demand
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Condizione: new. Questo è un articolo print on demand.
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Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermaniaBuchWeltWeit Ludwig Meier e.K.
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EUR 106,99
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Buch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power…to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy. 156 pp. Englisch.
Gain- Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
Pascal Meinerzhagen|Adam Teman|Robert Giterman|Noa Edri|Andreas Burg|Alexander Fish
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- Print on Demand
Da: moluna, Greven, Germaniamoluna
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EUR 89,99
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Gebunden. Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Provides novel gain-cell embedded DRAM (GC-eDRAM) designs for various low-power VLSI SoC applicationsModels the statistical retention time distribution of GC-eDRAM and validates the model by silicon measure…mentsDescribes various memory op.
Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
Meinerzhagen, Pascal; Teman, Adam; Giterman, Robert; Edri, Noa; Burg, Andreas; Fish, Alexander
- Rilegato
- Print on Demand
Da: Majestic Books, Hounslow, Regno UnitoMajestic Books
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EUR 144,74
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Condizione: New. Print on Demand.
Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
Meinerzhagen, Pascal; Teman, Adam; Giterman, Robert; Edri, Noa; Burg, Andreas; Fish, Alexander
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- Print on Demand
Da: Biblios, frankfurt am main, HESSE, GermaniaBiblios
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EUR 148,68
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Condizione: New. PRINT ON DEMAND.
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- Print on Demand
Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germaniabuchversandmimpf2000
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 106,99
EUR 60,00 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Buch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to p…ower-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 156 pp. Englisch.
