Isbn: 9783659907456 - performance optimization in network-on-chip: multi level network partitioning approach (5 risultati)

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  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing, 2016

    3659907456 / 9783659907456

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    Da: preigu, Osnabrück, Germaniapreigu

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    Taschenbuch. Condizione: Neu. Performance Optimization in Network-on-Chip | Multi Level Network Partitioning Approach | Asrani Lit (u. a.) | Taschenbuch | 80 S. | Englisch | 2016 | LAP LAMBERT Academic Publishing | EAN 9783659907456 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. …

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing Jun 2016, 2016

    3659907456 / 9783659907456

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    Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermaniaBuchWeltWeit Ludwig Meier e.K.

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    Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The increasing complexity of System-on-Chips (SoCs) has resulted in the bottlenecking of the system due to scalability problems in the bus system. This leads to the decrement of performance of future SoCs with more complex circuitries inside them. Network-on-Chips (NoCs) was proposed as one of the solutions to overcome these issues especially regarding the communication between Intellectual Properties (IP) in a chip. The fundamentals in designing NoC include the selection of network topologies, and hence, performance optimization is needed to ensure the full advantage of networking is taken. Therefore, multi-level Network Partitioning techniques are proposed to obtain the optimal design of networks based on its performance. The performance of a network is measured by its throughput, average queue size, waiting time and data loss. This technique is applied in a case study using MPEG-4 video application. The proposed technique is expected to enhance the performance of the NoC. 80 pp. Englisch.…

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing, 2016

    3659907456 / 9783659907456

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    Da: AHA-BUCH GmbH, Einbeck, GermaniaAHA-BUCH GmbH

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    Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The increasing complexity of System-on-Chips (SoCs) has resulted in the bottlenecking of the system due to scalability problems in the bus system. This leads to the decrement of performance of future SoCs with more complex circuitries inside them. Network-on-Chips (NoCs) was proposed as one of the solutions to overcome these issues especially regarding the communication between Intellectual Properties (IP) in a chip. The fundamentals in designing NoC include the selection of network topologies, and hence, performance optimization is needed to ensure the full advantage of networking is taken. Therefore, multi-level Network Partitioning techniques are proposed to obtain the optimal design of networks based on its performance. The performance of a network is measured by its throughput, average queue size, waiting time and data loss. This technique is applied in a case study using MPEG-4 video application. The proposed technique is expected to enhance the performance of the NoC.…

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing, 2016

    3659907456 / 9783659907456

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    Da: moluna, Greven, Germaniamoluna

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    EUR 31,27

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    Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Lit AsraniMuhamad Qaedi Edanan is a Bachelor in Electronic Engineering (Computer) from Universiti Malaysia Sarawak (UNIMAS). Asrani Lit is a Research Scientist at Department of Electrical and Electronic in UNIMAS.The increasing c.…

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing Jun 2016, 2016

    3659907456 / 9783659907456

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    Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germaniabuchversandmimpf2000

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    Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -The increasing complexity of System-on-Chips (SoCs) has resulted in the bottlenecking of the system due to scalability problems in the bus system. This leads to the decrement of performance of future SoCs with more complex circuitries inside them. Network-on-Chips (NoCs) was proposed as one of the solutions to overcome these issues especially regarding the communication between Intellectual Properties (IP) in a chip. The fundamentals in designing NoC include the selection of network topologies, and hence, performance optimization is needed to ensure the full advantage of networking is taken. Therefore, multi-level Network Partitioning techniques are proposed to obtain the optimal design of networks based on its performance. The performance of a network is measured by its throughput, average queue size, waiting time and data loss. This technique is applied in a case study using MPEG-4 video application. The proposed technique is expected to enhance the performance of the NoC.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 80 pp. Englisch.…