9783838307329 - Cost-effective Methods for High-speed Nanometer CMOS VLSI Design: Interconnect and Circuits di Akl, Charbel (6 risultati)

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Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The semiconductor industry has been following Moore s law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs. 132 pp. Englisch.

Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Akl CharbelCharbel Akl received a M.S. in Computer Engineering from University of Balamand, Lebanon, in 2004, and a PhD in Computer Engineering from University of Louisiana at Lafayette in 2008. After graduation, he joined Intel .

Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -The semiconductor industry has been following Moore's law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 132 pp. Englisch.

Taschenbuch. Condizione: Neu. Cost-effective Methods for High-speed Nanometer CMOS VLSI Design | Interconnect and Circuits | Charbel Akl | Taschenbuch | 132 S. | Englisch | 2010 | LAP LAMBERT Academic Publishing | EAN 9783838307329 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu Print on Demand.

Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The semiconductor industry has been following Moore s law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.