Isbn: 9789811010729 - high-level estimation and exploration of reliability for multi-processor system-on-chip (11 risultati)

Condizione: New. In.

Condizione: New.

Hardcover. Condizione: Brand New. 217 pages. 9.25x6.10x0.56 inches. In Stock.

Buch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.…

Condizione: New.

Hardcover. Condizione: New. NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

Condizione: new. Questo è un articolo print on demand.

Buch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. 220 pp. Englisch.…

Buch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 220 pp. Englisch.…

Condizione: New. Print on Demand.

Condizione: New. PRINT ON DEMAND.