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low power networks on chip (31 risultati)
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Low Power Networks-on-Chip
Da: Patrico Books, Apollo Beach, FL, U.S.A.
Valutazione del venditore 5 su 5 stelle
hardcover. Condizione: As New. Ships Out Tomorrow!
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EUR 9,36
EUR 105,00 shipping
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Aggiungi al carrelloCondizione: Hervorragend. Zustand: Hervorragend | Seiten: 287 | Sprache: Englisch | Produktart: Bücher | Keine Beschreibung verfügbar.
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EUR 9,36
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Aggiungi al carrelloCondizione: Sehr gut. Zustand: Sehr gut | Seiten: 287 | Sprache: Englisch | Produktart: Bücher | Keine Beschreibung verfügbar.
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EUR 9,36
EUR 105,00 shipping
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Aggiungi al carrelloCondizione: Sehr gut. Zustand: Sehr gut | Seiten: 287 | Sprache: Englisch | Produktart: Bücher | Keine Beschreibung verfügbar.
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Low Power Networks-on-Chip
Da: Ria Christie Collections, Uxbridge, Regno Unito
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EUR 111,14
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3D Networks-on-Chip Architecture Optimization for Low Power Design
Editore: LAP LAMBERT Academic Publishing, 2015
ISBN 10: 3659758132 ISBN 13: 9783659758133
Lingua: Inglese
EUR 61,60
EUR 70,00 shipping
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Aggiungi al carrelloTaschenbuch. Condizione: Neu. 3D Networks-on-Chip Architecture Optimization for Low Power Design | Michael Opoku Agyeman | Taschenbuch | 180 S. | Englisch | 2015 | LAP LAMBERT Academic Publishing | EAN 9783659758133 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.
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Low Power Networks-on-Chip
Da: Books Puddle, New York, NY, U.S.A.
Valutazione del venditore 4 su 5 stelle
Condizione: New. pp. 308.
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Low Power Networks-on-Chip
Da: Lucky's Textbooks, Dallas, TX, U.S.A.
Valutazione del venditore 5 su 5 stelle
EUR 149,17
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Low Power Networks-on-Chip
Da: Ria Christie Collections, Uxbridge, Regno Unito
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EUR 146,49
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Low Power Networks-on-Chip
Editore: Springer US, Springer New York, 2014
ISBN 10: 1489994378 ISBN 13: 9781489994370
Lingua: Inglese
EUR 111,53
EUR 62,35 shipping
Ships from Germania to U.S.A.Quantità: 1 disponibili
Aggiungi al carrelloTaschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
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Low Power Networks-on-Chip
Da: Mispah books, Redhill, SURRE, Regno Unito
Valutazione del venditore 4 su 5 stelle
EUR 167,35
EUR 28,61 shipping
Ships from Regno Unito to U.S.A.Quantità: 1 disponibili
Aggiungi al carrelloPaperback. Condizione: Like New. Like New. book.
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Low Power Networks-On-Chip
Da: Books Puddle, New York, NY, U.S.A.
Valutazione del venditore 4 su 5 stelle
Condizione: New. pp. 308.
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3D Networks-on-Chip Architecture Optimization for Low Power Design
Editore: LAP LAMBERT Academic Publishing, 2015
ISBN 10: 3659758132 ISBN 13: 9783659758133
Lingua: Inglese
Da: Mispah books, Redhill, SURRE, Regno Unito
Valutazione del venditore 4 su 5 stelle
EUR 181,49
EUR 28,61 shipping
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Aggiungi al carrellopaperback. Condizione: New. NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
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EUR 155,88
EUR 63,08 shipping
Ships from Germania to U.S.A.Quantità: 2 disponibili
Aggiungi al carrelloBuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issuesstill represent one of the limiting factors in integrating multi- and many-coreson a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.
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Low Power Networks-on-Chip
Da: Mispah books, Redhill, SURRE, Regno Unito
Valutazione del venditore 4 su 5 stelle
EUR 230,99
EUR 28,61 shipping
Ships from Regno Unito to U.S.A.Quantità: 1 disponibili
Aggiungi al carrelloHardcover. Condizione: Like New. Like New. book.
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3D Networks-on-Chip Architecture Optimization for Low Power Design
Editore: LAP LAMBERT Academic Publishing Jul 2015, 2015
ISBN 10: 3659758132 ISBN 13: 9783659758133
Lingua: Inglese
Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
Valutazione del venditore 5 su 5 stelle
EUR 64,90
EUR 23,00 shipping
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Aggiungi al carrelloTaschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip communication demands of future multi-core embedded systems. However, 3D NoCs have not been completely accepted into the mainstream due to issues such as the high cost and complexity of manufacturing 3D vertical wires, larger memory, area and power consumption of 3D NoC components than that of conventional 2D NoC. This thesis aims at optimizing 3D NoCs by modeling and evaluating alternate NoC topologies, routing algorithms and mapping techniques to achieve optimized area, power and performance parameters (latency and throughput). Particularly, novel 3D NoC router architectures and their possible combinations have been investigated with the aim of achieving lower area and power consumption of on-chip communication components with a minimal performance trade-off. This book investigates different heterogeneous 3D NoC architectures which combine 2D and 3D routers to improve area and energy efficiency of 3D NoCs with minimal performance degradation. 180 pp. Englisch.
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Low Power Networks-on-Chip (eng)
Da: Brook Bookstore On Demand, Napoli, NA, Italia
Valutazione del venditore 5 su 5 stelle
EUR 86,24
EUR 5,50 shipping
Ships from Italia to U.S.A.Quantità: Più di 20 disponibili
Aggiungi al carrelloCondizione: new. Questo è un articolo print on demand.
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3D Networks-on-Chip Architecture Optimization for Low Power Design
Editore: LAP LAMBERT Academic Publishing, 2015
ISBN 10: 3659758132 ISBN 13: 9783659758133
Lingua: Inglese
EUR 58,12
EUR 48,99 shipping
Ships from Germania to U.S.A.Quantità: Più di 20 disponibili
Aggiungi al carrelloCondizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Opoku Agyeman MichaelDr Michael Opoku Agyeman received the BSc. (Hons.) in electrical and electronics engineering from KNUST, Ghana, in 2008, and the MSc. degree in embedded and distributed systems from LSBU, London, in 2009. He rece.
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Low Power Networks-on-Chip (eng)
Da: Brook Bookstore On Demand, Napoli, NA, Italia
Valutazione del venditore 5 su 5 stelle
EUR 118,26
EUR 6,80 shipping
Ships from Italia to U.S.A.Quantità: Più di 20 disponibili
Aggiungi al carrelloCondizione: new. Questo è un articolo print on demand.
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Low Power Networks-on-Chip
Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
Valutazione del venditore 5 su 5 stelle
EUR 106,99
EUR 23,00 shipping
Ships from Germania to U.S.A.Quantità: 2 disponibili
Aggiungi al carrelloTaschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. 308 pp. Englisch.
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3D Networks-on-Chip Architecture Optimization for Low Power Design
Editore: LAP LAMBERT Academic Publishing Jul 2015, 2015
ISBN 10: 3659758132 ISBN 13: 9783659758133
Lingua: Inglese
Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germania
Valutazione del venditore 5 su 5 stelle
EUR 71,90
EUR 60,00 shipping
Ships from Germania to U.S.A.Quantità: 1 disponibili
Aggiungi al carrelloTaschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip communication demands of future multi-core embedded systems. However, 3D NoCs have not been completely accepted into the mainstream due to issues such as the high cost and complexity of manufacturing 3D vertical wires, larger memory, area and power consumption of 3D NoC components than that of conventional 2D NoC. This thesis aims at optimizing 3D NoCs by modeling and evaluating alternate NoC topologies, routing algorithms and mapping techniques to achieve optimized area, power and performance parameters (latency and throughput). Particularly, novel 3D NoC router architectures and their possible combinations have been investigated with the aim of achieving lower area and power consumption of on-chip communication components with a minimal performance trade-off. This book investigates different heterogeneous 3D NoC architectures which combine 2D and 3D routers to improve area and energy efficiency of 3D NoCs with minimal performance degradation.Books on Demand GmbH, Überseering 33, 22297 Hamburg 180 pp. Englisch.
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3D Networks-on-Chip Architecture Optimization for Low Power Design
Editore: LAP LAMBERT Academic Publishing, 2015
ISBN 10: 3659758132 ISBN 13: 9783659758133
Lingua: Inglese
EUR 71,90
EUR 61,43 shipping
Ships from Germania to U.S.A.Quantità: 1 disponibili
Aggiungi al carrelloTaschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip communication demands of future multi-core embedded systems. However, 3D NoCs have not been completely accepted into the mainstream due to issues such as the high cost and complexity of manufacturing 3D vertical wires, larger memory, area and power consumption of 3D NoC components than that of conventional 2D NoC. This thesis aims at optimizing 3D NoCs by modeling and evaluating alternate NoC topologies, routing algorithms and mapping techniques to achieve optimized area, power and performance parameters (latency and throughput). Particularly, novel 3D NoC router architectures and their possible combinations have been investigated with the aim of achieving lower area and power consumption of on-chip communication components with a minimal performance trade-off. This book investigates different heterogeneous 3D NoC architectures which combine 2D and 3D routers to improve area and energy efficiency of 3D NoCs with minimal performance degradation.
-
EUR 89,99
EUR 48,99 shipping
Ships from Germania to U.S.A.Quantità: Più di 20 disponibili
Aggiungi al carrelloCondizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architecturesApplies state-of-the-art, low-power design techniques to the design of .
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Low Power Networks-on-Chip
Editore: Springer-Verlag New York Inc., 2014
ISBN 10: 1489994378 ISBN 13: 9781489994370
Lingua: Inglese
Da: THE SAINT BOOKSTORE, Southport, Regno Unito
Valutazione del venditore 5 su 5 stelle
EUR 135,14
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Aggiungi al carrelloPaperback / softback. Condizione: New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days 474.
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Low Power Networks-on-Chip
Da: Majestic Books, Hounslow, Regno Unito
Valutazione del venditore 4 su 5 stelle
EUR 147,62
EUR 7,44 shipping
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Aggiungi al carrelloCondizione: New. Print on Demand pp. 308.
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Low Power Networks-on-Chip
Da: Biblios, Frankfurt am main, HESSE, Germania
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EUR 149,07
EUR 9,95 shipping
Ships from Germania to U.S.A.Quantità: 4 disponibili
Aggiungi al carrelloCondizione: New. PRINT ON DEMAND pp. 308.
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Low Power Networks-on-Chip
Editore: Springer US, Springer US Nov 2014, 2014
ISBN 10: 1489994378 ISBN 13: 9781489994370
Lingua: Inglese
Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germania
Valutazione del venditore 5 su 5 stelle
EUR 106,99
EUR 60,00 shipping
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Aggiungi al carrelloTaschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 308 pp. Englisch.
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Low Power Networks-On-Chip
Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
Valutazione del venditore 5 su 5 stelle
EUR 149,79
EUR 23,00 shipping
Ships from Germania to U.S.A.Quantità: 2 disponibili
Aggiungi al carrelloBuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issuesstill represent one of the limiting factors in integrating multi- and many-coreson a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings. 287 pp. Englisch.
-
EUR 128,41
EUR 48,99 shipping
Ships from Germania to U.S.A.Quantità: Più di 20 disponibili
Aggiungi al carrelloCondizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architecturesApplies state-of-the-art, low-power design techniques to the design of .
-
Low Power Networks-On-Chip
Da: Majestic Books, Hounslow, Regno Unito
Valutazione del venditore 4 su 5 stelle
EUR 210,14
EUR 7,44 shipping
Ships from Regno Unito to U.S.A.Quantità: 4 disponibili
Aggiungi al carrelloCondizione: New. Print on Demand pp. 308 Illus.
