Editore: Kluwer Academic Publishers.
Lingua: Inglese
Da: Antiquariat Thomas Haker GmbH & Co. KG, Berlin, Germania
Membro dell'associazione: GIAQ
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Aggiungi al carrelloHardcover. Condizione: Wie neu. Auflage: 2004. 309 S., Really new. Shrink wrapped. / Neuwertiger Zustand. In Folie verschweißt. Sprache: Englisch Gewicht in Gramm: 840.
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Aggiungi al carrelloHardcover. Condizione: Good. No Jacket. Pages can have notes/highlighting. Spine may show signs of wear. ~ ThriftBooks: Read More, Spend Less 1.54.
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Aggiungi al carrelloCondizione: New. pp. 316 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam.
Da: Biblios, Frankfurt am main, HESSE, Germania
EUR 44,93
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EUR 68,35
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Aggiungi al carrelloCondizione: Sehr gut. Zustand: Sehr gut - Neubindung, Buchkanten leicht angestossen, Buchschnitt leicht verkürzt, Auflage 2004 | Seiten: 300 | Sprache: Englisch | Produktart: Bücher.
EUR 78,87
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Aggiungi al carrelloHardcover. Condizione: Good. Connecting readers with great books since 1972! Used textbooks may not include companion materials such as access codes, etc. May have some wear or writing/highlighting. We ship orders daily and Customer Service is our top priority!
Da: Ria Christie Collections, Uxbridge, Regno Unito
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EUR 164,49
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Aggiungi al carrelloTaschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book presents the perspective of the project on a Paradigm Unifying System Specification Environments for proven Electronic design (PUS SEE) as conceived in the course of the research during 2002 -2003. The initial statement of the research was formulated as follows: The objective of PUSSEE is to introduce the formal proof of system properties throughout a modular system design methodology that integrates sub-systems co-verification with system refinement and reusability of virtual system components. This will be done by combining the UML and B languages to allow the verification of system specifications through the composition of proven sub-systems (in particular interfaces, using the VSIAISLIF standard). The link of B with C, VHDL and SystemC will extend the correct-by-construction design process to lower system-on-chip (SoC) development stages. Prototype tools will be developed for the code generation from UML and B, and existing B verification tools will be extended to supportIP reuse, according to the VSI Alliance work. The methodology and tools will be validated through the development of three industrial applications: a wireless mobile terminal-a telecom system-on-chip based on HIPERLANI2 protocol and an anti-collision module for automobiles. The problem was known to be hard and the scope ambitious. But the seventeen chapters that follow, describing the main results obtained demonstrate the success of the research, acknowledged by the European reviewers. They are released to allow the largest audience to learn and take benefit of.
EUR 178,14
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Aggiungi al carrelloGebunden. Condizione: New. Presents the perspective of the project on a Paradigm Unifying System Specification Environments for proven Electronic design (PUSSEE)Shows the success of research, as acknowledged by the European reviewersIntroduces the formal proof of sys.
EUR 209,66
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Da: Mispah books, Redhill, SURRE, Regno Unito
EUR 234,10
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Aggiungi al carrelloBuch. Condizione: Neu. Neuware - This book presents the perspective of the project on a Paradigm Unifying System Specification Environments for proven Electronic design (PUS SEE) as conceived in the course of the research during 2002 -2003. The initial statement of the research was formulated as follows: The objective of PUSSEE is to introduce the formal proof of system properties throughout a modular system design methodology that integrates sub-systems co-verification with system refinement and reusability of virtual system components. This will be done by combining the UML and B languages to allow the verification of system specifications through the composition of proven sub-systems (in particular interfaces, using the VSIAISLIF standard). The link of B with C, VHDL and SystemC will extend the correct-by-construction design process to lower system-on-chip (SoC) development stages. Prototype tools will be developed for the code generation from UML and B, and existing B verification tools will be extended to supportIP reuse, according to the VSI Alliance work. The methodology and tools will be validated through the development of three industrial applications: a wireless mobile terminal-a telecom system-on-chip based on HIPERLANI2 protocol and an anti-collision module for automobiles. The problem was known to be hard and the scope ambitious. But the seventeen chapters that follow, describing the main results obtained demonstrate the success of the research, acknowledged by the European reviewers. They are released to allow the largest audience to learn and take benefit of.
EUR 268,35
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Aggiungi al carrelloPaperback. Condizione: Brand New. 300 pages. 9.25x6.00x0.71 inches. In Stock.
Da: Mispah books, Redhill, SURRE, Regno Unito
EUR 308,87
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Aggiungi al carrelloHardcover. Condizione: Like New. Like New. book.
Da: moluna, Greven, Germania
EUR 137,26
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Aggiungi al carrelloCondizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Presents the perspective of the project on a Paradigm Unifying System Specification Environments for proven Electronic design (PUSSEE)Shows the success of research, as acknowledged by the European reviewersIntroduces the formal proof of sys.
Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
EUR 160,49
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Aggiungi al carrelloTaschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book presents the perspective of the project on a Paradigm Unifying System Specification Environments for proven Electronic design (PUS SEE) as conceived in the course of the research during 2002 -2003. The initial statement of the research was formulated as follows: The objective of PUSSEE is to introduce the formal proof of system properties throughout a modular system design methodology that integrates sub-systems co-verification with system refinement and reusability of virtual system components. This will be done by combining the UML and B languages to allow the verification of system specifications through the composition of proven sub-systems (in particular interfaces, using the VSIAISLIF standard). The link of B with C, VHDL and SystemC will extend the correct-by-construction design process to lower system-on-chip (SoC) development stages. Prototype tools will be developed for the code generation from UML and B, and existing B verification tools will be extended to support IP reuse, according to the VSI Alliance work. The methodology and tools will be validated through the development of three industrial applications: a wireless mobile terminal-a telecom system-on-chip based on HIPERLANI2 protocol and an anti-collision module for automobiles. The problem was known to be hard and the scope ambitious. But the seventeen chapters that follow, describing the main results obtained demonstrate the success of the research, acknowledged by the European reviewers. They are released to allow the largest audience to learn and take benefit of. 312 pp. Englisch.
Da: Majestic Books, Hounslow, Regno Unito
EUR 219,51
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Aggiungi al carrelloCondizione: New. Print on Demand pp. ix + 300.
Da: Biblios, Frankfurt am main, HESSE, Germania
EUR 222,44
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Aggiungi al carrelloCondizione: New. PRINT ON DEMAND pp. ix + 300.