Built-In Self-Test for Input/Output Buffers: FPGAs & SOCs - Brossura

Vemula, Sudheer

Brossura

ISBN 10: 384337015X ISBN 13: 9783843370158

Casa editrice: LAP LAMBERT Academic Publishing, 2010

Riassunto

Programmable Input/Output (I/O) cells are an integral part of any Field Programmable Gate Array (FPGA). The resources associated with the programmable I/O cells are increasing as newer architectures of FPGAs are being developed and this increases the importance of testing them. A general Built-In Self-Test (BIST) architecture to test the programmable I/O cells in FPGAs or associated with the FPGA core of System-on-Chip (SoC) implementations is proposed. The I/O cells are tested for various modes of operation along with their associated programmable routing resources. The proposed BIST architecture has been implemented and verified on Atmel AT94K10 and AT94K40 SoCs. A total of 161 and 303 configuration downloads are required to test the I/O cells of AT94K10 and AT94K40 devices, respectively. The use of an embedded processor for dynamic partial reconfiguration reduced the number of configuration downloads to three for both the AT94K10 and AT94K40 devices. The implementation of dynamic partial reconfiguration gave a speed up of 99.39 times in test time and a reduction in configuration memory storage requirements by 101 times for AT94K40 devices.

Su questo libro

L'autore

Masters in VLSI Testing at Auburn University, Auburn, AL. Worked at Altera Corp. & NVIDIA Corp. as a Test Development engineer and Design For Test Engineer respectively.

Dettagli dell'edizione

• Editore: LAP LAMBERT Academic Publishing
• Data di pubblicazione: 2010
• Lingua: Inglese
• ISBN 10: 384337015X
• ISBN 13: 9783843370158
• Rilegatura: Copertina flessibile
• Numero di pagine: 100
• Contatto del produttore: non disponibile
• Persona responsabile: KreGa Onlinehandel GmbH; 4950000000000; info@krega-onlinehandel.de; ; Birkenweg 31; Brakel; 33034; Germania