Sinossi
This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation.
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Low Power Asynchronous Logic design for Viterbi Decoders
Editore:
LAP LAMBERT Academic Publishing Sep 2018, 2018
ISBN 10: 6139851297
ISBN 13: 9786139851294
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Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germania
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Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation. 56 pp. Englisch. Codice articolo 9786139851294
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Low Power Asynchronous Logic design for Viterbi Decoders
Editore:
LAP LAMBERT Academic Publishing, 2018
ISBN 10: 6139851297
ISBN 13: 9786139851294
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Da: Revaluation Books, Exeter, Regno Unito
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Paperback. Condizione: Brand New. 56 pages. 8.66x5.91x0.13 inches. In Stock. Codice articolo zk6139851297
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Low Power Asynchronous Logic design for Viterbi Decoders
Editore:
LAP LAMBERT Academic Publishing, 2018
ISBN 10: 6139851297
ISBN 13: 9786139851294
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Da: moluna, Greven, Germania
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Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Sakthivel T. Kalavathi DeviDr T. Kalavathi Devi completed her UG and PG in GCT, Coimbatore. Her areas of interest include VLSI Design, low power circuits, electronics system design. She has published papers in reputed journals and in. Codice articolo 385874302
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Low Power Asynchronous Logic design for Viterbi Decoders
Editore:
LAP LAMBERT Academic Publishing Sep 2018, 2018
ISBN 10: 6139851297
ISBN 13: 9786139851294
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Taschenbuch
Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germania
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Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 56 pp. Englisch. Codice articolo 9786139851294
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Low Power Asynchronous Logic design for Viterbi Decoders
Editore:
LAP LAMBERT Academic Publishing, 2018
ISBN 10: 6139851297
ISBN 13: 9786139851294
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Da: AHA-BUCH GmbH, Einbeck, Germania
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Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation. Codice articolo 9786139851294
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Low Power Asynchronous Logic design for Viterbi Decoders
Editore:
LAP LAMBERT Academic Publishing, 2018
ISBN 10: 6139851297
ISBN 13: 9786139851294
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Da: preigu, Osnabrück, Germania
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Taschenbuch. Condizione: Neu. Low Power Asynchronous Logic design for Viterbi Decoders | T. Kalavathi Devi Sakthivel (u. a.) | Taschenbuch | 56 S. | Englisch | 2018 | LAP LAMBERT Academic Publishing | EAN 9786139851294 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. Codice articolo 114835060
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